Samsung Unveils UFS 5.0 Storage, Claims Industry’s Fastest with 10.8GB/s Speeds
  While advancing its next-generation HBM development, Samsung is also pushing forward on the NAND front, unveiling what it claims is the industry’s first and fastest Universal Flash Storage (UFS) 5.0 solution. According to Samsung, the device delivers sequential read speeds of up to 10.8 GB/s and write speeds of up to 9.5 GB/s, more than doubling the performance of the previous UFS 4.1 standard.  Building on this performance leap, Samsung said mass production is scheduled to begin in the fourth quarter of this year, with capacities of up to 1TB. As noted by Chosun Biz, the solution is based on JEDEC’s latest embedded storage standard, UFS 5.0, and is built on the company’s ninth-generation V-NAND technology.  According to its press release, Samsung’s UFS 5.0 is designed to enable more seamless and efficient AI experiences on next-generation mobile devices, ranging from flagship smartphones to XR headsets and AI wearables. The improved performance is expected to reduce latency and accelerate response times when running large language models (LLMs) in on-device AI applications.  UFS 5.0 Key Specs in Focus  Generative AI is rapidly migrating from cloud environments to on-device deployment, driving a sharp increase in the volume of data required for local processing. As a result, storage is shifting from a passive data repository into a core infrastructure layer that directly supports AI computation.  Against this backdrop, Samsung’s new storage solution delivers sequential read speeds of up to 10.8 GB/s and sequential write speeds of up to 9.5 GB/s, more than doubling the performance of the previous UFS 4.1 standard. On the other hand, the product’s power efficiency, according to the press release, has also been improved by over 40% compared with Samsung’s UFS 4.1 solution, driven by a range of architectural enhancements including clock gating and multi-voltage design technologies.  The device also features a more compact design. According to Samsung, the UFS 5.0 solution comes in an ultra-compact package measuring just 7.5mm × 13mm × 0.9mm, making it 16.7% smaller than its predecessor. The reduced form factor enhances design flexibility and improves internal space efficiency across a wide range of applications, including smartphones, wearables, and extended reality (XR) devices.
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Release time:2026-06-25 10:40 reading:143 Continue reading>>
UMC May Net Profit Surges 203% YoY as Utilization Strength Drives Earnings Upside
  Ahead of its planned second-half price increases, UMC is already riding a profit upswing fueled by robust utilization rates. The foundry posted May revenue of NT$22.94 billion, up 17.8% year-over-year, while net profit soared 203% to NT$8.45 billion, translating into EPS of NT$0.68, according to its latest unaudited earnings disclosure.  Notably, May EPS alone nearly matched the NT$0.71 generated in the whole second quarter of last year, and accounted for roughly 53% of the NT$1.29 earned in the first quarter of 2026, according to the Economic Daily News and MoneyDJ.  The strong momentum in May aligns with UMC’s Q2 guidance. According to Central News Agency, wafer shipments are expected to rise 7%–9% QoQ, with utilization reaching 81%–83%. ASPs are projected to increase 1%–3%, supporting gross margin close to 30%.  Industry sources cited by the Economic Daily News further indicate UMC’s overall capacity utilization averaged around 85% in the second quarter of 2026. The company’s 12-inch fab in Tainan has yet to reach full utilization, while its Singapore facility remains fully loaded and its Xiamen fab is operating near full capacity, the report suggests.  Meanwhile, demand for specialty 8-inch process technologies continues to strengthen, with product lines including PMICs maintaining stable order intake, as noted by the report.  UMC has further cemented its position in the mature-node foundry segment, with 22/28nm accounting for 34% of wafer revenue, followed by 40nm at 18%, according to its latest quarterly earnings. Geographically, Asia Pacific remained the largest market at 65% of sales, while North America contributed 21%.  Intel Collaboration Rumors  While market speculation around a potential UMC–Intel partnership on 3nm technologies has intensified, UMC said it does not comment on rumors or market speculation, as noted by TechNews.  More concretely, the 12nm collaboration between UMC and Intel is progressing smoothly. According to the report, the jointly developed 12nm FinFET platform is on track for mass production in 2027. The program is being advanced in close collaboration, with process validation expected to complete in 2026 before production is transferred to Intel’s Ocotillo fab in Arizona, the report adds.  Additionally, the Economic Daily News also notes that UMC is focusing on silicon photonics and advanced packaging. The company has secured silicon photonics process licensing and is leveraging its proprietary SOI process and 8-inch volume production experience to advance a 12-inch silicon photonics platform. Meanwhile, embedded deep trench capacitor products have entered mass production and begun shipment, and have been designed into international customers’ supply chains, according to the report.
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Release time:2026-06-25 10:38 reading:149 Continue reading>>
SanDisk Goes Beyond HBF: Patent Bonds Processor onto NAND Tile, with HBM Stacks on Shared Interposer
  While SanDisk is speeding up the development of High Bandwidth Flash (HBF), a next-generation architecture that vertically stacks NAND, the company is also advancing additional memory concepts aimed at addressing structural capacity constraints.  According to a U.S. patent (US 12,430,274 B2) filed and published by SanDisk earlier, the proposed design integrates a multi-core processor directly onto a CBA (CMOS Bonded to Array) memory tile — which itself combines a large NAND flash array with a CMOS logic layer.  The integrated stack is then mounted on an interposer, with stacks of HBM semiconductor dies affixed around one or more sides of the combined stack, SanDisk notes.  Rationale Behind the Design  The design rationale behind SanDisk’s approach, as noted by Wccftech, is partly driven by the inherent limitations of HBM, particularly its relatively constrained capacity, as well as the challenges that HBF has yet to fully address, including latency, power efficiency, and system-level integration complexity.  To overcome HBM’s capacity ceiling, SanDisk previously introduced its HBF architecture, which adopts a similar concept to HBM by vertically stacking multiple layers of NAND flash and connecting them via through-silicon vias (TSVs) to form a unified memory stack, according to Wccftech.  While current HBM solutions typically offer 32–64GB per stack, HBF is designed to scale significantly higher, with reported capacity reaching up to 4TB. According to SanDisk, HBF is capable of closely matching HBM’s bandwidth while delivering 8-16x the capacity of HBM at a similar cost.  However, despite NAND offering higher capacity at a lower cost, Wccftech also points out that it is positioned further from the compute die, resulting in slower data access compared to DRAM-based architectures. In response, SanDisk’s latest patent, as highlighted by the report, proposes a 3D stacking design in which a NAND flash tile, built using a CBA structure, is positioned beneath a compute tile such as an AI accelerator or GPU.  Under this configuration, HBM DRAM would still be integrated on the same interposer, but would serve a distinct role within the overall memory-compute hierarchy, according to Wccftech. As highlighted by the report, this architecture allows HBM to handle immediate, high-speed memory operations, while the NAND flash layer within the memory tile is used for read/write-intensive workloads and large-scale data storage.
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Release time:2026-06-23 10:58 reading:176 Continue reading>>
Intel Taps SK hynix Ex-CEO as Foundry EVP to Lead Advanced Packaging Push as EMIB, HBI Scale Up
  Intel CEO Lip-Bu Tan is accelerating the company’s foundry ambitions, continuing to recruit seasoned talent from across the chip industry. The latest move is the appointment of Seok-Hee Lee as Executive Vice President of Intel Foundry, according to an Intel announcement on June 18.  Notably, Lee joins Intel after serving as president and CEO of SK On and previously leading SK hynix. A semiconductor industry veteran, he also held engineering leadership roles at Intel and in academia, bringing deep expertise in advanced process technologies and large-scale manufacturing, according to the press release.  Reporting directly to Tan, Lee will oversee advanced packaging, system integration, back-end technology development, and manufacturing, as noted by the company. Intel said the appointment is aimed at strengthening its system-level innovation capabilities and supporting the next phase of its foundry expansion.  Tan also underscored Lee’s pivotal role in advancing Intel’s next-generation packaging strategy.“As we prepare to scale advanced packaging technologies, including EMIB-T and HBI, for high-volume production, Seok-Hee is the ideal leader to drive the growth of this strategically important business,” Tan said.  The appointment, as Reuters points out, comes after U.S. President Donald Trump announced earlier that Apple had agreed to collaborate with Intel on designing and manufacturing chips in the United States, providing a potential boost to Intel’s foundry business.  A previous Reuters report, citing The Information, also reported that Google has tapped Intel to manufacture more than 3 million TPUs in 2028, while NVIDIA is evaluating Intel’s 18A process and advanced packaging technologies for a next-generation multi-die GPU design.  Meanwhile, Intel Foundry EVP Naga Chandrasekaran will continue reporting to CEO Lip-Bu Tan, overseeing front-end technology development and manufacturing as Intel accelerates the ramp of Intel 18A, Intel 14A and future process nodes. He will also retain responsibility for design enablement and customer-facing business operations, supporting Intel Foundry’s long-term growth.  Intel’s Talent Offensive Continues  Lee’s appointment marks the latest in a series of high-profile hires since Lip-Bu Tan took the helm at Intel. Reuters notes that the company bolstered its foundry ambitions in April by recruiting Samsung foundry veteran Shawn Han to support its contract manufacturing business.  The hiring drive began earlier. In late 2025, Intel brought in former TSMC senior vice president Wei-Ren Lo as executive vice president overseeing manufacturing and packaging amid controversy surrounding alleged sub-2nm trade secrets. Intel said Lo’s return was part of its broader transformation effort, with the veteran executive bringing back nearly two decades of experience gained at Intel before joining TSMC.
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Release time:2026-06-22 10:51 reading:196 Continue reading>>
Apple A22 Pro May Adopt 1.4nm in 2028; TSMC Remains Primary Supplier, Intel Reportedly Considered
  Apple is expected to use TSMC’s 2nm for its A20 and A20 Pro chips, but industry discussions are already shifting to the A22 Pro and a potential move to 1.4nm. According to Bloomberg, Apple is expected to adopt a 1.4nm process for the A22 Pro, which is slated for high-end iPhone models in 2028. While TSMC is expected to remain Apple’s primary manufacturing partner, the report notes that the company is also evaluating Intel as a potential secondary production source.  Based on the reported timeline, the A21 Pro is expected to remain on TSMC’s 2nm, potentially transitioning to the enhanced N2P variant, which offers incremental improvements over N2, according to Wccftech.  Wccftech also notes that costs could rise significantly, with TSMC’s 1.4nm wafers estimated to cost around US$45,000 each. As a result, the report suggests that only the A22 Pro, rather than the standard A22, will be manufactured on the 1.4nm node.  As noted by MacRumors, current rumors suggest Intel could manufacture lower-end chips for products such as the iPad and Mac. At the same time, Intel CEO Lip-Bu Tan is seeking to revive the company’s foundry business by focusing on leading-edge nodes. According to TechPowerUp, Intel expects its 14A node to enter risk production in 2028, followed by high-volume manufacturing in 2029.  Beyond the possibility of Apple adopting TSMC’s 1.4nm node for its A22 chips, the company is reportedly preparing three major product launches for late 2027. According to 9to5Mac, citing Bloomberg, these include a 20th-anniversary iPhone featuring a nearly edge-to-edge display and curved glass that wraps around the sides, a second-generation foldable iPhone, and AirPods equipped with built-in cameras.  TSMC’s A14 Roadmap Takes Shape  TSMC has been accelerating construction of its 1.4nm fab at the Central Taiwan Science Park. According to Economic Daily News, foundation piling for the first phase has largely been completed, with progress reportedly ahead of schedule. Trial production could begin as early as 3Q27, with mass production targeted for the second half of 2028.  Compared with N2, A14 is expected to deliver a 10–15% performance improvement at the same power level, or reduce power consumption by 25–30% at the same performance level, while increasing logic density by more than 20%, according to TSMC.
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Release time:2026-06-18 10:15 reading:475 Continue reading>>
SK hynix Reportedly Pulls Forward HBM4E Sample Timeline, Eyeing June–July Shipments to Key Customers
  Samsung announced the start of HBM4E sampling in late May and later unveiled an HBM5 mock-up for the first time at COMPUTEX 2026. Against this backdrop, rival SK hynix is also stepping up its next-generation HBM push, with South Korean media outlet Newsis reporting that the memory giant has secured positive results in HBM4E development and is nearing sample shipments to key customers.  Notably, certain analysts cited by the report expect SK hynix to begin HBM4E sample shipments as early as this month, or by July at the latest. The company had previously guided that sampling would start in the second half of the year, suggesting the timeline is now being pulled forward, the report adds.  As Newsis notes, next-generation HBM is highly customized for customers, and earlier sample shipments enable faster performance validation and optimization—ultimately translating into a strategic edge in securing final mass production orders.  Beyond sampling timelines, broader supply and pricing dynamics are also shifting, which may give early movers key advantages. According to TrendForce, as the market enters 2Q26, negotiations between buyers and suppliers have shifted toward HBM4 supply agreements for 2027, which is expected to become the market’s mainstream project generation. The shift underscores how both Samsung and SK hynix are accelerating HBM4 and HBM4E development amid tightening market cycles.  SK hynix HBM4E Specs Under Spotlight  As highlighted by Newsis, SK hynix’s HBM4E is likely to be used in NVIDIA’s next-generation AI accelerator, Rubin Ultra, set for release next year. In line with this platform upgrade, TrendForce notes that NVIDIA’s Rubin Ultra is expected to further increase HBM capacity per GPU to 384GB.  Against this backdrop of rising system-level requirements, HBM4E specifications are also being pushed higher across the stack. According to Newsis, SK hynix’s HBM4E core die is expected to adopt a 1c DRAM process node, compared with the 1b node used in HBM4. In addition, The Chosun Daily previously reported that the company is likely to use TSMC’s 3nm process for its HBM4E logic die, aiming to challenge Samsung’s 4nm design.  On the competitive front, Samsung Electronics completed the world’s first shipment of HBM4E samples in late May, supplying them to NVIDIA, according to Yonhap News.  Samsung’s HBM4E combines a 1c DRAM core die with a 4nm foundry-based base die, delivering speeds of up to 14Gbps per pin and peaking at 16Gbps, equivalent to a maximum bandwidth of 4TB/s, the report notes.
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Release time:2026-06-16 10:43 reading:390 Continue reading>>
Tesla Elon Musk Discusses TeraFab at ASML Conference; Project Expected to Spur EUV Tool Orders
  Elon Musk is expanding his ambitions beyond EVs, AI, and space technology with TeraFab, a large-scale semiconductor manufacturing project in Texas. According to CNBC, during an ASML conference on Thursday, Tesla CEO Elon Musk outlined his TeraFab vision. As the only provider of a crucial EUV machine, ASML is widely expected to become a key supplier for the Texas-based fabrication plant.  Joining remotely at ASML’s annual technology conference, Musk took part in a fireside chat with CEO Christophe Fouquet. While the event was limited to employees, ASML confirmed Musk’s participation, the report states.  ASML also signaled support for the initiative. As noted by Reuters, the company said that Musk and his team are becoming part of the broader semiconductor ecosystem and that many companies, including ASML, will collaborate on the project.  For the project, SpaceX and its partner Tesla will invest an initial US$55 billion, with total investment potentially rising to US$119 billion if fully built out, as noted by Reuters.  TeraFab Fuels Equipment Demand Across the Supply Chain  In May, ASML CEO Christophe Fouquet said he had spoken directly with Elon Musk about the TeraFab semiconductor project, according to Tom’s Hardware, citing Reuters. While Fouquet did not disclose details of the discussions, he said projects such as TeraFab and Starlink are expected to place growing pressure on equipment suppliers’ capacity in the coming years.  Maeil Business Newspaper also notes that expectations for a surge in equipment demand have risen after Musk discussed the TeraFab project at the ASML Technology Conference. The report adds that ASML’s core equipment is expected to be essential to the project.  South Korean equipment makers are also seeking to capitalize on the opportunity. According to Seoul Economic Daily, Hanmi Semiconductor announced on June 12 that it will invest KRW 50 billion in SpaceX. The report says Hanmi aims to strengthen ties with SpaceX and position itself to supply key equipment for TeraFab.  Interest in the project has been building for months. According to Bloomberg, Musk’s team had reportedly contacted major chip equipment suppliers, including Applied Materials, Tokyo Electron, and Lam Research, regarding the planned facility. Sources said staff working for the Tesla-SpaceX venture had requested pricing and delivery information for a range of semiconductor manufacturing tools.
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Release time:2026-06-15 10:48 reading:382 Continue reading>>
Lenovo Reportedly Set for July Price Hikes Across Product Portfolio as Memory Costs Pressure PC Market
  With memory prices remaining elevated, consumer electronics could be heading for another round of price increases. Chinese media outlet Lanjinger.com, citing sources familiar with the matter, reports that Lenovo plans to raise prices across its product lineup from July, broadly in line with the previous round of increases, after the 618 shopping festival ends.  Notably, Lanjinger.com highlights this would not be Lenovo’s first price hike this year, pointing to March when the PC maker issued nationwide price adjustment notices and raised retail prices for some models by over RMB 1,000. The report adds it has already urged distributors to lock in inventory and secure current pricing ahead of the upcoming increase, with a formal notice expected to be issued by the end of June.  The pricing pressure is spreading across the PC industry. Dell, as highlighted by the report, has already raised prices on certain products as well, with server prices increasing 20%–40%. Prices for desktops, notebooks, and workstations are also expected to see further significant hikes by July, the report suggests.  A separate report from Sina also suggests the sharp rise in costs has put pressure on the entire PC industry, prompting several major vendors to begin raising prices as early as six months ago. Dell, according to Sina, increased prices across its commercial PC portfolio in late 2025, with hikes ranging from 10% to 30%.  Memory Price Surge Drives PC Cost Pressure  Surging memory prices have become a key driver behind rising costs for PC brands. Lanjinger.com, citing TrendForce data, reports that cumulative spot price increases for DRAM and NAND flash have exceeded 300%. By May 2026, the average price of PC-grade DDR4 8Gb memory had climbed to US$20, the highest level since TrendForce began tracking the market, according to the report.  Against this backdrop, Taipei Times, citing TrendForce’s latest forecast, reports that global notebook shipments are now expected to decline 13% YoY in 2026, as soaring memory prices and tight CPU supply weigh on demand in the second half—marking a sharper downturn than the 9.4% drop projected in January.
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Release time:2026-06-11 10:33 reading:506 Continue reading>>
Samsung, NVIDIA Deepen Ties as Talks Reportedly Expand to HBM5 Next Year and Next-Gen Groq Chips
  Following Jensen Huang’s high-profile meetings with SK hynix during his South Korea visit, Samsung Electronics Vice Chairman Jun Young-hyun met with the NVIDIA CEO on June 8 to discuss potential cooperation in HBM and foundry services. According to The Chosun Daily, Jun said the discussions focused on collaboration in HBM and foundry. He added that the near-term priority is to ensure stable supplies of HBM4 and SOCAMM this year, while the two companies also discussed longer-term collaboration beginning next year, including HBM4E, foundry services, and HBM5.  Samsung, NVIDIA Expand Foundry Cooperation  On the foundry front, Samsung Electronics is in discussions with NVIDIA on next-generation chip production using its advanced process technologies, including the Drive AGX Thor autonomous driving chip and the Groq language processing unit (LPU), according to Seoul Economic Daily.  Jun said Samsung is manufacturing NVIDIA’s autonomous driving and Groq chips using 4nm and 8nm nodes, according to ZDNet. He added that the partnership also extends to next-generation Groq chips.  As highlighted by Seoul Economic Daily, Samsung currently manufactures the third-generation Groq LPU (LP30) on its 4nm process. Jun’s remarks suggest the company is also in position to produce the next-generation LP40, despite industry expectations that TSMC could secure the order through its advanced packaging strengths.  Samsung Details Memory Portfolio for NVIDIA  On the memory front, Samsung Electronics is supplying HBM4 (6th-generation) memory with data transfer speeds exceeding 11.7 Gbps per pin for NVIDIA’s Vera Rubin platform, according to Yonhap News. The company is also providing LPDDR5X-based SOCAMM2 modules for the Vera CPU, as well as its PCIe Gen6-based PM1763 storage solution.  Yonhap News adds that Samsung’s HBM4E combines DRAM core dies with a proprietary 4nm foundry base die, enabling operating speeds of 14 Gbps per pin and achieving up to 16 Gbps in testing.  Meanwhile, Vice Chairman Jeon stopped short of confirming whether Samsung Electronics and NVIDIA would sign a long-term memory supply agreement, saying Samsung would do its utmost as a key partner to support NVIDIA’s success, according to Newspim.  NVIDIA CEO Jensen Huang also discussed the company’s partnership with Samsung during a Q&A session following the NVIDIA Korea AI Ecosystem Reception. According to Dealsite, Huang said NVIDIA and Samsung have long collaborated in the Application-Specific Integrated Circuit (ASIC) sector and are jointly developing new ASIC products. He added that the two companies also share a long history of cooperation in memory technologies.
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Release time:2026-06-10 10:37 reading:525 Continue reading>>
Largan Expands CPO Push, Plans September Fiber Array Pilot Line, Eyes 2027 Revenue Contribution
  Taiwan’s Largan Precision, a key optical lens supplier in Apple’s supply chain, is expanding into CPO. According to Liberty Times, Chairman Adam Lin said after the company’s shareholders’ meeting today that Largan plans to establish an automated pilot production line for its fiber array (FA) products in September and may invite a potential major customer to visit the facility.  Lin said the company has developed a proprietary technology that enables conventional V-grooves and optical fibers to be assembled into high-precision FA products. He noted that tolerance stack-up between V-grooves and optical fibers has been a key challenge for the industry, often forcing competitors to rely on the highest-precision V-grooves and optical fibers to achieve the required accuracy. Largan, however, can use less-than-perfect components to produce FA products with precision below 0.3 microns, outperforming the industry’s typical range of 0.5 to 0.8 microns, the report highlights.  Largan made its first appearance at Computex this year, showcasing CPO-related solutions and expanding into optical components such as FAUs (fiber array units) and MLAs (microlens arrays). The move is widely viewed as an important signal that the company is seeking new high-margin growth drivers beyond its core smartphone lens business, as noted by China Times.  The company’s investment in fiber arrays aligns with growing demand for CPO technologies. TrendForce forecasts that co-packaged optics (CPOs) will steadily increase their share of optical communication modules in AI data centers, with penetration potentially reaching 35% by 2030.  Largan Sees Multi-Row FAs as Next Growth Driver  FAUs (fiber array units) combine FAs with components such as microlens arrays (MLAs) and prism microlens arrays (PMLAs). According to Liberty Times, Lin expects single-row products to remain the industry’s primary source of demand through 2028. Over the next three to four years, however, rising computing requirements are expected to drive a gradual shift toward two-row, four-row, and eventually eight-row configurations, the report notes. Lin said this transition would play to Largan’s strengths, citing the company’s multilayer stacking and high-precision technologies as key differentiators.  Largan Eyes 2027 FA Revenue as Qualification Process Advances  Looking ahead, Lin said FA products could begin contributing to revenue in 2027 if Largan successfully completes customer qualification, the Liberty Times report notes. However, because the products have yet to enter mass production, the company is not currently able to estimate yields or gross margins. Meanwhile, preparations for low-volume production are expected to take about six months to one year. Lin said the production line will be highly automated to improve process precision and manufacturing capacity while reducing reliance on labor-intensive production.
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Release time:2026-06-10 10:29 reading:515 Continue reading>>

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