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SK Group Chairman Says Abnormal Memory Prices Should Fall; AI Chip Demand Seen Up 60–100% Next Year

　　The recent surge in memory prices has drawn comments from SK Group Chairman Chey Tae-won, who also chairs SK hynix, one of the biggest beneficiaries of the boom. According to ETNews, Chey, who also serves as chairman of the Korea Chamber of Commerce and Industry (KCCI), said current memory prices are abnormally high and warned that if prices remain elevated, PC and mobile device prices will continue to rise, with those higher costs ultimately weighing on consumer demand.　　As noted by Maeil Business Newspaper, Chey said demand for AI semiconductors is expected to increase by 60% to 100% in 2027 from 2026, while the broader memory semiconductor market is also projected to grow by at least 50% to 60% over the same period. However, he noted that few companies are meaningfully expanding supply, meaning the supply-demand gap is likely to widen further. This suggests that while the AI investment boom is driving memory prices higher, it could ultimately place greater pressure on downstream industries.　　He argued that rising prices are not a healthy sign for the market, adding that prices should fall because current levels are abnormal. He also warned that PC and mobile manufacturers cannot continue passing higher memory costs on to consumers. This suggests that while the AI investment boom is driving memory prices higher, it could ultimately place greater pressure on downstream industries.　　Chey also argued that memory companies should not restrict supply to keep prices elevated. As noted by Maeil Business Newspaper, he said limiting production to maintain high prices is not a sustainable strategy, adding that expanding supply to grow the overall market—even at the expense of slightly lower margins—would generate greater long-term benefits. He further warned that persistently high prices could attract new competitors and prompt governments to intervene.　　However, Chey acknowledged that expanding supply will not be easy. According to Maeil Business Newspaper, increasing production of advanced AI memory requires significant investment and time to build manufacturing capacity, while shortages of equipment and skilled personnel remain key constraints. Although the industry is working to maximize output, he said demand is growing much faster, raising concerns that memory prices may continue to rise rather than fall. As ETNews notes, Chey said the top priority is to expand memory production capacity wherever possible, including in Yongin, the Honam region, and the U.S.　　Chey’s comments align with SK hynix CEO Kwak Noh-jung’s assessment of the industry’s supply-demand outlook. According to Reuters, Kwak said the global memory industry is heading for its worst-ever supply shortage in 2027, with memory demand expected to outpace production capacity well into the next decade despite aggressive capacity expansion.　　Chey on AI Infrastructure and Long-Term Growth　　Beyond the memory market, Chey also predicted that even if the current supply shortage is partially eased, AI-related bottlenecks will shift to other parts of the infrastructure stack. According to ETNews, Chey said electrical equipment for energy infrastructure is already in short supply, and as AI adoption accelerates, shortages could eventually extend to power cables and even the raw materials needed to manufacture data center cables.　　Looking further ahead, Chey said the ongoing wave of AI infrastructure investment is expected to eventually lower the cost of generating AI tokens, as noted by ETNews. Once the industry enters a token economy in which AI is converted into productivity for real-world work and services, he believes a self-sustaining AI ecosystem will emerge.

Key word：

SK Group

Release time：2026-07-21 10:29 reading：163 Continue reading>>

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Samsung Reportedly Developing 4nm GAIA AI PC Chip; Mass Production Targeted as Early as 2027

　　Samsung is reportedly preparing to enter the AI PC chip market. According to Hankyung, industry sources say Samsung Electronics’ System LSI Business under the Device Solutions (DS) Division is developing GAIA, a 4nm AI accelerator for AI PCs. Prototype chips have reportedly already been provided to major customers, including Lenovo and HP, for performance validation, with mass production targeted as early as 2027.　　Samsung plans to pair GAIA with processing-in-memory (PIM), a next-generation DRAM technology that performs computations directly within memory, as the report indicates. Unlike traditional PC processors, GAIA is designed specifically for AI workloads, with an optimized NPU architecture aimed at efficiently handling generative AI tasks.　　The reported move follows Samsung’s earlier attempt to enter the PC chip market 14 years ago with an Exynos application processor that powered Samsung Chromebooks in 2012. However, it failed to break Intel’s dominance and withdrew from the business roughly two years later.　　AI PC Chip Competition Intensifies　　Samsung’s reported move positions it alongside a growing number of companies targeting the AI PC market. The report says the segment remains in its early stages and has yet to produce a dominant player as the AI agent era begins to emerge. Companies including NVIDIA, Qualcomm, Intel, and Huawei are already competing in the space. NVIDIA unveiled its next-generation RTX Spark AI PC chip in May, while Qualcomm first introduced the Snapdragon X Elite in 2023 before expanding its lineup with the entry-level Snapdragon C.　　EBN News says Samsung Electronics aims to differentiate itself by leveraging its leadership in memory alongside the AI chip design expertise gained from developing smartphone APs and mobile NPUs. Industry observers believe that combining AI accelerators with processing-in-memory (PIM) technology could enhance both AI processing performance and power efficiency.　　Industry observers cited by Hankyung say the success of Samsung’s AI PC chip initiative will depend largely on its ability to secure major customers and bring the product to market. If the company achieves mass production and builds a stable supply chain, the business could emerge as a key growth driver, helping the System LSI Business address its long-standing structural losses.　　Despite the growth opportunity, Samsung’s expansion into the AI accelerator market may also present strategic challenges. Hankyung notes that companies including NVIDIA and Qualcomm, which Samsung is expected to compete against in the AI PC market, are also among Samsung Foundry’s key customers.

Key word：

Samsung

Release time：2026-07-13 13:53 reading：317 Continue reading>>

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Intel Reportedly Weighs Dual-Side Power Delivery for 14A2 to Boost Chip Density in Race With TSMC, Samsung

　　Intel is reportedly refining its 1.4nm roadmap with a new power delivery architecture. According to ETNews, sources say the company originally planned to rely exclusively on its PowerDirect back-side power delivery network (BSPDN) for the baseline 14A node. However, Intel is now reportedly considering a dual-side architecture for the follow-on 14A2 process that combines both front-side and back-side power delivery.　　The report says the architectural change is driven by lithography limitations as Intel pushes the pitch of its lowest metal layer (M0) to around 21nm, where stochastic defects become increasingly difficult to manage.　　Intel has previously said it aims to increase chip density by 1.3× over 18A to compete with TSMC’s N2/A14 and Samsung’s SF2Z. While 14A targets an M0 pitch of approximately 28nm, industry analysis cited by the report suggests the follow-on 14A2 could reduce it to around 21nm. The report says the resulting density gains would help justify the use of High-NA EUV lithography systems, despite requiring double patterning, which cost hundreds of billions of Korean won.　　The challenge, however, is that shrinking circuit lines below 21nm causes interconnect resistance to rise exponentially. The report says the nano Through-Silicon Via (nTSV) infrastructure built for back-side power delivery alone may no longer meet the current density requirements of the transistors, leading to severe IR drop, or voltage loss. Intel is therefore expected to keep the back-side power delivery network as the primary power path while repurposing portions of the front-side metal layers to carry supplemental power and clock signals.　　The report says the hybrid architecture is a design compromise aimed at preserving sufficient power margin as Intel pushes toward more aggressive scaling while confronting lithography limitations. Although it adds routing complexity, the approach is viewed as necessary to achieve the targeted 21nm M0 pitch.　　Intel’s reported move also comes as TSMC advances its Super Power Rail (SPR) backside power delivery roadmap, with A16 slated for volume production in 2027 and A12 targeted for 2029, both incorporating the technology for AI and HPC applications, according to Tom’s Hardware.　　Roadmap Comparison　　The ETNews report also highlights Intel’s tight development timeline. According to its roadmap, the 14A process is scheduled to enter risk production in 2028, followed by volume production in 2029. Intel is also expected to distribute version 0.9 of its 14A Process Design Kit (PDK) to external customers in October, the report adds.　　By the time Intel reaches risk production, however, TSMC is expected to already be shipping commercial products built on its A14 process. The report notes that TSMC had already achieved stable yields on its N2 process during 2025–2026 and entered the market in line with Apple’s product launch schedule. As for Samsung, The Elec reports that the company has recently reaffirmed plans to begin mass production of its 1.4nm process in 2029, followed by the enhanced SF1.4+ node in 2030.

Key word：

Intel

Release time：2026-07-07 11:21 reading：383 Continue reading>>

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Huawei Expands Tau Scaling Law V2 Paper, Highlighting LogicFolding Path to Ascend AI Chips in 2030

　　Two months after Huawei introduced the Tau (τ) Scaling Law in May, the company on July 3 disclosed additional details on an updated version, including further implementation insights and performance-related data. Notably, the V2 version of Time Scaling Theory for Multi-Level Electronic Systems (Tau Law) also outlines a roadmap extending LogicFolding beyond mobile SoCs into AI accelerators, including Huawei’s Ascend 990 expected around 2030.　　Kirin 2026 Delivers Density Gain　　In the near term, Kirin 2026 serves as the first validation platform for the dual-layer LogicFolding architecture. Chinese media outlets Guacha and mrjjxw.com, citing the paper published on ChinaXiv platform under the Chinese Academy of Sciences, report that compared with the 2025 Kirin 9030 Pro baseline, the Kirin 2026 achieves a transistor density increase from 155 MTr/mm² to 238 MTr/mm², representing a gain of approximately 53.5%.　　The paper, cited by Guacha, also notes that achieving a similar gain through conventional geometric scaling would typically require about three years. As reported by Stdaily, Huawei’s first smartphone powered by the Kirin 2026 processor is expected to debut this fall, marking the first real-world test of the technology in the market.　　According to Huawei, LogicFolding is a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers. On a mobile SoC, LogicFolding delivers a 55% stepwise increase in transistor density and a 41% reduction in power consumption at equivalent performance at a fixed device node, the company notes.　　(Credit: Huawei)　　Guacha further cites the V2 version of Time Scaling Theory for Multi-Level Electronic Systems (Tau Law), which projects logic folding will evolve from localized critical-path optimization to full multi-layer architectures over the next decade, with each package integrating three or more active layers.　　The shift, according to the report, is driven by low-temperature hybrid bonding, which relaxes inter-layer thermal constraints, and TSV landing point migration from upper metals to M6, freeing over 30% of routing resources. Under this trajectory, transistor density is projected to scale toward 400 MTr/mm² and beyond between 2026 and 2035, the report suggests.　　Next Phase: LogicFolding in Ascend AI Chips　　Notably, the V2 version of Time Scaling Theory for Multi-Level Electronic Systems identifies Huawei’s Ascend AI chips as the next application of LogicFolding. According to Guacha, while the technology could enable Kirin processors to boost CPU clock speeds toward 4GHz and beyond, it is also expected to extend to the Ascend 990 AI accelerator around 2030. The report further notes that 3D folding is expected to become the primary carrier of the α architecture through 2035.　　According to Huawei, in AI system designs, a co-designed stack—combining memory-semantic Unified Bus fabric, near-package Hi-ONE optical I/O, and edge-to-surface 3D folding—is projected to deliver more than 100× growth in hardware integration by 2035.

Key word：

Huawei

Release time：2026-07-07 11:18 reading：411 Continue reading>>

Trade news

Samsung, NVIDIA Deepen Ties as Talks Reportedly Expand to HBM5 Next Year and Next-Gen Groq Chips

　　Following Jensen Huang’s high-profile meetings with SK hynix during his South Korea visit, Samsung Electronics Vice Chairman Jun Young-hyun met with the NVIDIA CEO on June 8 to discuss potential cooperation in HBM and foundry services. According to The Chosun Daily, Jun said the discussions focused on collaboration in HBM and foundry. He added that the near-term priority is to ensure stable supplies of HBM4 and SOCAMM this year, while the two companies also discussed longer-term collaboration beginning next year, including HBM4E, foundry services, and HBM5.　　Samsung, NVIDIA Expand Foundry Cooperation　　On the foundry front, Samsung Electronics is in discussions with NVIDIA on next-generation chip production using its advanced process technologies, including the Drive AGX Thor autonomous driving chip and the Groq language processing unit (LPU), according to Seoul Economic Daily.　　Jun said Samsung is manufacturing NVIDIA’s autonomous driving and Groq chips using 4nm and 8nm nodes, according to ZDNet. He added that the partnership also extends to next-generation Groq chips.　　As highlighted by Seoul Economic Daily, Samsung currently manufactures the third-generation Groq LPU (LP30) on its 4nm process. Jun’s remarks suggest the company is also in position to produce the next-generation LP40, despite industry expectations that TSMC could secure the order through its advanced packaging strengths.　　Samsung Details Memory Portfolio for NVIDIA　　On the memory front, Samsung Electronics is supplying HBM4 (6th-generation) memory with data transfer speeds exceeding 11.7 Gbps per pin for NVIDIA’s Vera Rubin platform, according to Yonhap News. The company is also providing LPDDR5X-based SOCAMM2 modules for the Vera CPU, as well as its PCIe Gen6-based PM1763 storage solution.　　Yonhap News adds that Samsung’s HBM4E combines DRAM core dies with a proprietary 4nm foundry base die, enabling operating speeds of 14 Gbps per pin and achieving up to 16 Gbps in testing.　　Meanwhile, Vice Chairman Jeon stopped short of confirming whether Samsung Electronics and NVIDIA would sign a long-term memory supply agreement, saying Samsung would do its utmost as a key partner to support NVIDIA’s success, according to Newspim.　　NVIDIA CEO Jensen Huang also discussed the company’s partnership with Samsung during a Q&A session following the NVIDIA Korea AI Ecosystem Reception. According to Dealsite, Huang said NVIDIA and Samsung have long collaborated in the Application-Specific Integrated Circuit (ASIC) sector and are jointly developing new ASIC products. He added that the two companies also share a long history of cooperation in memory technologies.

Key word：

Samsung

Release time：2026-06-10 10:37 reading：766 Continue reading>>

Trade news

Intel Says 18A May Reach Strong Margins by 2027; Notebook Chips on the Node Mark Fastest Ramp in 5 Years

　　Intel is betting heavily on 18A to support the company’s turnaround plan. According to The Register, Chief Financial Officer David Zinsner said that early last year Intel faced the challenge of trying to improve both performance and yield at the same time. The company later shifted its focus to stabilizing performance first, and with that objective largely achieved, it is now concentrating on improving yield month by month.　　Zinsner said Intel’s goal is to achieve yield levels that support strong margins, adding that the company is currently ahead of schedule to reach that target by the end of 2027, as the report highlights. He added that after Lip-Bu Tan joined the company, Intel began sharing more manufacturing data with its vendors. The increased collaboration helped improve yields and made a dramatic difference.　　Looking beyond 18A, Zinsner also expressed confidence in Intel’s 14A. According to the report, he said the company has adopted a more aggressive approach than it did with 18A, adding that yield and performance metrics are currently ahead of where 18A was at the same stage of development.　　Intel 3 and 18A Supply Set to Rise Amid Strong CPU Demand　　In addition to providing an update on Intel’s manufacturing roadmap, Zinsner highlighted growing supply from Intel 3 and 18A, according to Seeking Alpha. As cited by the report, he said Intel expects a meaningful increase in supply from both Intel 3 and 18A over the coming quarters to meet rising demand. He added that 18A-based notebook processors are ramping quickly and represent the company’s fastest-ramping product launch in at least the past five years.　　The company is also seeing rising CPU demand. According to The Register, Zinsner said it remains difficult to predict the full extent of future growth, but he expects the market to be substantial. He said the key challenge at present is supply, adding that Intel sees sufficient demand in the market and should be able to grow data center revenue meaningfully if it executes successfully on planned supply ramps.

Key word：

Intel

Release time：2026-06-05 10:40 reading：637 Continue reading>>

Trade news

SMIC Founder Says China May Gain Edge in Niche Chips as 80% of Demand Lies Outside Advanced Nodes

　　As China pushes to strengthen its chip industry, Richard Chang, founder of SMIC, China’s largest foundry, suggests that success in semiconductors is not solely about winning the 2nm or 3nm race, with niche markets potentially emerging as a key competitive advantage for China. According to STAR Market Daily, Chang said that niche markets have become a key breakthrough point for China’s semiconductor industry, adding that advancing in specialized market segments could help strengthen the country’s overall chip capabilities.　　SMIC remains limited to the 7nm node due to its reliance on older DUV lithography equipment. However, Richard Chang’s emphasis on niche markets suggests that the company’s mature-node technologies could still find meaningful opportunities across a range of applications, as noted by Wccftech.　　SMIC Founder Highlights Opportunity Beyond Advanced Nodes　　As noted by STAR Market Daily, Richard Chang argued that semiconductor success should not be defined solely by achieving 3nm or 2nm nodes, describing such thinking as a misconception and highlighting niche markets as a key opportunity for China’s chip industry.　　Chang further noted that advanced nodes account for less than 20% of the global semiconductor market by product volume, while more than 80% of demand comes from mature-node and specialty-process segments. According to Chang, many niche markets still dominated by overseas players could represent key breakthrough opportunities for Chinese semiconductor companies.　　The trend may already be emerging across parts of the supply chain. According to TrendForce, with Taiwanese foundries shifting capacity and raising prices, customers in HV processes and CIS applications are increasingly turning to Chinese foundries for more stable pricing and capacity availability. This order migration has been evident since the second half of 2025, driving strong demand for 90 nm-and-above 12-inch wafers among Chinese players.　　Beyond Large Models: Richard Chang Highlights Edge AI Potential　　In addition, Richard Chang argued that edge AI and scenario-driven applications remain underappreciated opportunities within the broader AI landscape. As STAR Market Daily notes, Chang said sectors such as industrial control, automotive electronics, and wearable devices could create strong demand for application-specific semiconductor solutions, offering startups room to pursue differentiated strategies outside direct competition with global AI giants.

Key word：

SMIC

Release time：2026-05-12 10:24 reading：770 Continue reading>>

Trade news

Apple Reportedly Eyes Samsung, Intel U.S. Foundry for Core Chips Amid TSMC Constraints, Supply Diversification

　　Apple is reportedly weighing the possibility of having some of its core device chips manufactured by Samsung and Intel. According to Bloomberg, citing sources, the company has held preliminary discussions on using the two as alternative production partners for its main processors—potentially providing a second sourcing option alongside its longstanding supplier, TSMC.　　Sources say the company has held early-stage discussions with Intel about leveraging its foundry services, while Apple executives have also visited a Samsung facility under construction in Texas that is expected to produce advanced chips.　　That said, the report notes that neither effort has led to any orders so far. Engagements with both suppliers remain at a preliminary stage, as Apple continues to have reservations about adopting non-TSMC manufacturing technologies.　　One of the key drivers behind Apple’s potential shift is supply constraints at TSMC, according to Bloomberg. As the report notes, Apple executives addressed the issue during the company’s quarterly earnings call last week, indicating that limited chip availability for iPhone and Mac devices is currently weighing on growth.　　In early 2026, Tim Cook identified access to advanced-node manufacturing as the main bottleneck for Apple’s iPhone output, according to CNBC. He noted that production is constrained by limited capacity for the company’s A-series and M-series system-on-chip (SoC) chips, which are fabricated on TSMC’s 3nm process.　　In addition, it also aims to maintain at least two suppliers for key components, allowing Apple to strengthen its negotiating leverage on pricing while reducing the risk of supply disruptions, Bloomberg adds.　　Apple’s Reported Supplier Talks May Open Door for Intel Comeback, Samsung Gains　　Apple’s talks with both companies reportedly began before the most recent supply constraints emerged. As Bloomberg notes, collaborating with Intel could offer an added advantage, potentially strengthening Apple’s ties with the Donald Trump administration. As for Samsung, the report indicates that it has already been working on supplying more peripheral components for Apple’s devices, including power management parts.　　In an August 2025 press release, Apple also announced a partnership with Samsung to co-develop a new chip manufacturing technology at Samsung’s Austin fab. Citing industry sources, Business Korea adds that the chip Samsung is expected to produce will likely be used as an image sensor in future iPhones and other Apple products.　　Separately, industry momentum appears to be building around Intel’s foundry push. According to Commercial Times, major tech firms including Google and Apple are weighing a shift to Intel’s foundry. The report adds that Apple’s M-series chips are evaluating Intel’s 18A-P node.　　Apple’s potential shift could provide a boost to both Samsung and Intel. As the report notes, securing external customers for its foundry business is central to Intel’s turnaround strategy under CEO Lip-Bu Tan. Winning Apple as a client would mark a major milestone for Tan and could help draw in additional business. Samsung, meanwhile, would also stand to gain significantly from an endorsement by Apple.

Key word：

Apple

Release time：2026-05-06 14:44 reading：763 Continue reading>>

Trade news

ROHM Launches an Ultra-Compact Wireless Power Chipset for Wearables

　　ROHM has developed a wireless power supply IC chipset consisting of the receiver - ML7670 - and transmitter - ML7671 - compatible with Near Field Communication (NFC) technology for compact wearables such as smart rings and smart bands as well as peripheral devices like smart pens.　　The smart ring market has seen rapid growth in recent years, primarily in healthcare and fitness applications. However, for extremely small ring-shaped devices worn on the finger, wired charging is impractical, while conventional Qi wireless charging standard is difficult to implement due to constraints such as coil size. This has driven increased demand for a proximity-based power transfer method capable of reliably charging ultra-compact devices.　　In response, NFC-based charging, which operates at the high-frequency 13.56MHz band that enables antenna miniaturization, is attracting increased attention, with adoption accelerating in next-generation wearables. Following the successful commercialization of the 1W ML7660/ML7661, ROHM has developed the ML7670/ML7671 chipset optimized for even smaller devices.　　This new chipset builds on the proven receiver - ML7660 - and transmitter - ML7661. The maximum power transfer is specified at 250mW, while peripheral components such as the switching MOSFETs required to supply power to the charging IC are built in. The result is a solution optimized for both mounting area and power transfer efficiency in the power class demanded by compact wearable devices, especially smart rings.　　The ML7670 power receiver IC achieves a maximum power transfer efficiency of 45% in the 250mW low output range – all in an industry-leading form factor of just 2.28 × 2.56 × 0.48mm. A key feature of the new chipset is superior performance that surpasses the efficiency of comparable products in the same class by optimizing elements such as coil matching, rectifier circuitry, and reduced losses in switching devices.　　What's more, all firmware required for wireless power delivery is embedded directly within the IC, eliminating the need for a host MCU. This significantly reduces board space along with development workload in device design.　　Compliance with NFC Forum (WLC 2.0) enables power transfer while maintaining compatibility with existing devices, positioning the chipset as a core element in the expanding NFC wireless power ecosystem.　　The new chipset is already in mass production. Furthermore, it has been adopted in SOXAI RING 2, the latest model launched on December 10th, 2025, by SOXAI, Inc. (“SOXAI” is pronounced “SOK-sai”.), the Japanese developer and distributor of the original sleep monitoring ring SOXAI RING. Evaluation boards and reference designs are also offered to facilitate integration. For more information, please contact a sales representative or submit an inquiry via the contact page on ROHM’s website.　　Going forward, ROHM will continue to promote device development that leverages miniaturization and low-power consumption technologies essential for wearable devices, contributing to improved user convenience and the continued growth of the wearable market.　　Specifications　　Case Study: SOXAI RING 2 Adoption Example SOXAI RING is the only smart ring for sleep management developed in Japan capable of accurately capturing and analyzing sleep data. It incorporates cutting-edge technologies such as an optical vital sensor, temperature sensor, accelerometer, Bluetooth® Low Energy communication, and NFC wireless charging functionality.　　The latest model, SOXAI RING 2, is equipped with Deep Sensing™, a proprietary photoplethysmography (PPG) sensor that significantly improves measurement accuracy, enabling the visualization of physical health changes with far greater depth and precision.　　Bluetooth® is a registered trademark of Bluetooth SIG, Inc. in the US.　　Deep Sensing™ is a trademark or registered trademark of SOXAI, Inc.

Key word：

ROHM

Release time：2026-04-29 10:03 reading：715 Continue reading>>

Murata expands lineup of high cutoff frequency <span style='color:red'>chip</span> common mode choke coils in 0504-inch size for automotive high-speed differential interfaces

Trade news

Murata expands lineup of high cutoff frequency chip common mode choke coils in 0504-inch size for automotive high-speed differential interfaces

　　Murata Manufacturing Co., Ltd. (hereinafter ‘Murata’) has added a high cutoff frequency*1 product to its lineup of noise suppression components, the 0504-inch size (1.25 x1.0mm) chip common mode choke coils ‘‘DLM11C_HH2 Series’’ (hereinafter, ‘the product’), suitable for automotive high-speed differential interfaces such as LVDS*2, SerDes*3, USB, and HDMI. Murata has already started mass production of this product.　　*1High cutoff frequency: Reduces high-frequency noise.　　*2LVDS (Low Voltage Differential Signaling): An interface used for LCD panels.　　*3SerDes (Serializer/Deserializer): Circuits that convert between the serial and parallel signals in each direction.　　In recent years, the automotive market has seen multiple USB ports installed in each vehicle seat as interfaces for connecting smartphones and PCs, and data transfer speeds have increased from conventional USB 2.0 to Gbps-class USB 3.2. For these differential interfaces, common mode noise suppression is essential, and small common mode choke coils that support high-speed signals are required. In response, Murata developed this product using proprietary lamination technology to reduce high-frequency noise above 7.5 GHz in a compact 0504-inch size.　　Specifications　　*4AEC-Q200: One of the standards defined by the Automotive Electronics Council (AEC).

Key word：

Murata

Release time：2025-11-10 17:12 reading：1138 Continue reading>>

model	brand	Quote
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor
MC33074DR2G	onsemi
BD71847AMWV-E2	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor

model	brand	To snap up
ESR03EZPJ151	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
BU33JA2MNVX-CTL	ROHM Semiconductor
BP3621	ROHM Semiconductor
TPS63050YFFR	Texas Instruments
IPZ40N04S5L4R8ATMA1	Infineon Technologies

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