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Samsung’s 2Q Operating Profit Soars 1,810% to Record KRW 89.4T, Reportedly Surpassing NVIDIA and Apple

　　Amid surging DRAM and NAND prices, Samsung’s newly released second-quarter earnings guidance once again exceeded market expectations. According to the the company, cited by Hankyung, preliminary second-quarter operating profit reached KRW 89.4 trillion (US$65.6 billion), up 1,810.3% year over year. According to News 1, this would translate into an operating profit margin of 52.3%.　　Hankyung notes that the result marks Samsung’s highest quarterly operating profit on record, extending its record-breaking earnings streak to three consecutive quarters. ZDNet further highlights that the figure surpasses the quarterly operating profits of U.S. tech giants NVIDIA and Apple.　　Samsung’s record-breaking performance marks the highest quarterly operating profit ever reported by a global IT company, according to ZDNet, surpassing NVIDIA’s previous record of US$53.5 billion (approximately KRW 81.9 trillion) posted in the first quarter of fiscal 2027 (ended April 2026).　　The scale of the earnings surge is further underscored by comparisons with Samsung’s past performance. The company posted operating profit of just KRW 4.7 trillion in the same period last year, while its projected 2Q26 operating profit alone surpassed Samsung’s cumulative operating profit over the entire three-year period from 2023 to 2025, according to Reuters.　　Meanwhile, the company’s preliminary second-quarter revenue came in at roughly KRW 171 trillion, up 129.3% from a year earlier, Hankyung notes.　　Memory Prices Fuel Samsung’s Record Quarter　　The strong results were primarily driven by Samsung’s booming memory semiconductor business within its Device Solutions (DS) division, with industry observers noting that the company has been a major beneficiary of surging memory prices.　　According to ZDNet, average selling prices (ASPs) reportedly climbed more than 50% quarter over quarter for DRAM and over 60% for NAND. A separate ZDNet report also points out that the momentum is expected to continue, as Samsung Electronics is negotiating aggressively with customers to raise its third-quarter DRAM ASP by as much as 20% from the previous quarter.　　This strong performance aligns with TrendForce’s latest memory pricing survey, which indicates that the DRAM market will remain extremely tight in the third quarter of 2026, with contract DRAM prices expected to rise another 13–18%.　　However, Reuters also notes that despite another strong quarter expected from its memory business, losses in Samsung’s foundry and System LSI operations are likely to deepen, as employee bonus expenses continue to be allocated across the broader semiconductor division.

Key word：

Samsung

Release time：2026-07-08 13:16 reading：146 Continue reading>>

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Intel Reportedly Weighs Dual-Side Power Delivery for 14A2 to Boost Chip Density in Race With TSMC, Samsung

　　Intel is reportedly refining its 1.4nm roadmap with a new power delivery architecture. According to ETNews, sources say the company originally planned to rely exclusively on its PowerDirect back-side power delivery network (BSPDN) for the baseline 14A node. However, Intel is now reportedly considering a dual-side architecture for the follow-on 14A2 process that combines both front-side and back-side power delivery.　　The report says the architectural change is driven by lithography limitations as Intel pushes the pitch of its lowest metal layer (M0) to around 21nm, where stochastic defects become increasingly difficult to manage.　　Intel has previously said it aims to increase chip density by 1.3× over 18A to compete with TSMC’s N2/A14 and Samsung’s SF2Z. While 14A targets an M0 pitch of approximately 28nm, industry analysis cited by the report suggests the follow-on 14A2 could reduce it to around 21nm. The report says the resulting density gains would help justify the use of High-NA EUV lithography systems, despite requiring double patterning, which cost hundreds of billions of Korean won.　　The challenge, however, is that shrinking circuit lines below 21nm causes interconnect resistance to rise exponentially. The report says the nano Through-Silicon Via (nTSV) infrastructure built for back-side power delivery alone may no longer meet the current density requirements of the transistors, leading to severe IR drop, or voltage loss. Intel is therefore expected to keep the back-side power delivery network as the primary power path while repurposing portions of the front-side metal layers to carry supplemental power and clock signals.　　The report says the hybrid architecture is a design compromise aimed at preserving sufficient power margin as Intel pushes toward more aggressive scaling while confronting lithography limitations. Although it adds routing complexity, the approach is viewed as necessary to achieve the targeted 21nm M0 pitch.　　Intel’s reported move also comes as TSMC advances its Super Power Rail (SPR) backside power delivery roadmap, with A16 slated for volume production in 2027 and A12 targeted for 2029, both incorporating the technology for AI and HPC applications, according to Tom’s Hardware.　　Roadmap Comparison　　The ETNews report also highlights Intel’s tight development timeline. According to its roadmap, the 14A process is scheduled to enter risk production in 2028, followed by volume production in 2029. Intel is also expected to distribute version 0.9 of its 14A Process Design Kit (PDK) to external customers in October, the report adds.　　By the time Intel reaches risk production, however, TSMC is expected to already be shipping commercial products built on its A14 process. The report notes that TSMC had already achieved stable yields on its N2 process during 2025–2026 and entered the market in line with Apple’s product launch schedule. As for Samsung, The Elec reports that the company has recently reaffirmed plans to begin mass production of its 1.4nm process in 2029, followed by the enhanced SF1.4+ node in 2030.

Key word：

Intel

Release time：2026-07-07 11:21 reading：190 Continue reading>>

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Huawei Expands Tau Scaling Law V2 Paper, Highlighting LogicFolding Path to Ascend AI Chips in 2030

　　Two months after Huawei introduced the Tau (τ) Scaling Law in May, the company on July 3 disclosed additional details on an updated version, including further implementation insights and performance-related data. Notably, the V2 version of Time Scaling Theory for Multi-Level Electronic Systems (Tau Law) also outlines a roadmap extending LogicFolding beyond mobile SoCs into AI accelerators, including Huawei’s Ascend 990 expected around 2030.　　Kirin 2026 Delivers Density Gain　　In the near term, Kirin 2026 serves as the first validation platform for the dual-layer LogicFolding architecture. Chinese media outlets Guacha and mrjjxw.com, citing the paper published on ChinaXiv platform under the Chinese Academy of Sciences, report that compared with the 2025 Kirin 9030 Pro baseline, the Kirin 2026 achieves a transistor density increase from 155 MTr/mm² to 238 MTr/mm², representing a gain of approximately 53.5%.　　The paper, cited by Guacha, also notes that achieving a similar gain through conventional geometric scaling would typically require about three years. As reported by Stdaily, Huawei’s first smartphone powered by the Kirin 2026 processor is expected to debut this fall, marking the first real-world test of the technology in the market.　　According to Huawei, LogicFolding is a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers. On a mobile SoC, LogicFolding delivers a 55% stepwise increase in transistor density and a 41% reduction in power consumption at equivalent performance at a fixed device node, the company notes.　　(Credit: Huawei)　　Guacha further cites the V2 version of Time Scaling Theory for Multi-Level Electronic Systems (Tau Law), which projects logic folding will evolve from localized critical-path optimization to full multi-layer architectures over the next decade, with each package integrating three or more active layers.　　The shift, according to the report, is driven by low-temperature hybrid bonding, which relaxes inter-layer thermal constraints, and TSV landing point migration from upper metals to M6, freeing over 30% of routing resources. Under this trajectory, transistor density is projected to scale toward 400 MTr/mm² and beyond between 2026 and 2035, the report suggests.　　Next Phase: LogicFolding in Ascend AI Chips　　Notably, the V2 version of Time Scaling Theory for Multi-Level Electronic Systems identifies Huawei’s Ascend AI chips as the next application of LogicFolding. According to Guacha, while the technology could enable Kirin processors to boost CPU clock speeds toward 4GHz and beyond, it is also expected to extend to the Ascend 990 AI accelerator around 2030. The report further notes that 3D folding is expected to become the primary carrier of the α architecture through 2035.　　According to Huawei, in AI system designs, a co-designed stack—combining memory-semantic Unified Bus fabric, near-package Hi-ONE optical I/O, and edge-to-surface 3D folding—is projected to deliver more than 100× growth in hardware integration by 2035.

Key word：

Huawei

Release time：2026-07-07 11:18 reading：176 Continue reading>>

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Kioxia Begins BiCS 10 NAND Sampling, Reportedly Targets 2027 Mass Production at Kitakami Fab

　　Shortly after signaling summer sampling plans for its next-generation NAND, Kioxia on July 3 announced it has begun sample shipments of 1Tb (terabit) TLC (Triple-Level Cell) memory devices based on its 10th-generation BiCS FLASH 3D NAND technology. According to the company, the products will be manufactured at its Kitakami Plant Fab 2 in Iwate Prefecture, Japan.　　According to Nikkei, Kioxia plans to begin BiCS 10 NAND mass production in 2027. Performance has been significantly upgraded, with data transfer speeds reaching 4.8 gigabits per second—about 30% faster than the previous generation. Memory density has increased by 60%, while read power efficiency has improved by roughly 30%, Nikkei reports.　　Notably, The Japan Times reports that the new product, designed for solid-state drives (SSDs), is central to Kioxia’s strategy to capitalize on surging AI data center storage demand while reducing its reliance on smartphone-focused products, including those supplied to Apple.　　BiCS 10 Key Highlights: 332-Layer, CBA Technology　　As reported by EE Times Japan, a key highlight of Kioxia’s 10th-generation BiCS FLASH is the strategic choice of a 332-layer architecture. Traditionally, the NAND industry has improved bit density and reduced costs by pushing toward higher layer counts, and competitors of Kioxia are also advancing development of products exceeding 400 layers, the report notes.　　However, citing management, the report notes that excessive scaling of layer counts can create new challenges. According to Atsushi Inoue, General Manager of the Memory Business Division at Kioxia, at very high stack levels—such as above 400 layers—power consumption tends to increase as more memory layers are activated during read and write operations. In addition, further stacking may require thinner cell layers, which can reduce charge retention and raise concerns over long-term reliability.　　Notably, Kioxia’s 332-layer NAND structure, according to EE Times Japan, can reduce cost per gigabyte by around 10% versus 400-plus-layer designs, while also delivering roughly 10% better power efficiency and about 35% higher memory cell reliability.　　Another key feature of Kioxia 10th-generation BiCS FLASH is the continued use of CBA (CMOS directly Bonded to Array) technology, EE Times Japan suggests. Kioxia first introduced CBA in the 8th generation, which reportedly allowed the company to achieve interface speeds of 3.6Gb/s. According to Inoue, both the 9th and 10th generations now deliver 4.8Gb/s interface performance, extending Kioxia’s lead over rivals by roughly one year.　　Rivals Speed up NAND Moves　　Notably, Kioxia’s progress comes as its South Korean rivals accelerate aggressive NAND capacity moves. On July 2, SK hynix announced plans to invest a total of 100 trillion won in Cheongju, with 80 trillion won allocated to its M17 NAND production facility, according to Chosun Biz.　　CEO Kwak Noh-jung said NAND demand is rising rapidly while supply remains constrained, adding that Cheongju provides the fastest and most efficient base for SK hynix to build a new NAND fab, the report notes. According to SK hynix, construction of M17 is scheduled to begin next year, with operations targeted to commence in the first half of 2029.　　Meanwhile, an April report from The Bell also suggested that Samsung plans to establish a new NAND production line at its Pyeongtaek Campus Plant 5 (P5), where the cleanroom is scheduled to be completed next year. If confirmed, this would mark the company’s first major NAND capacity expansion since P3, the report added.

Key word：

Kioxia

Release time：2026-07-06 13:07 reading：180 Continue reading>>

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Samsung Reportedly Seeks Up to 20% 3Q26 DRAM Price Increase; LPDDR Hikes May Exceed 20%

　　Samsung is reportedly pushing for another wave of memory price increase in 3Q26. According to ZDNet, Samsung Electronics is negotiating aggressively with customers to raise its third-quarter DRAM average selling price (ASP) by as much as 20% from the previous quarter. An industry source added that LPDDR, which is facing severe supply bottlenecks across both the server and mobile markets, could also see price hikes exceeding 20%, although it remains unclear whether customers will accept the full increases.　　Samsung’s pricing push comes as the broader DRAM market remains exceptionally tight. According to TrendForce, supply conditions are expected to stay extremely constrained in the third quarter of 2026. However, weaker demand from consumer applications and the impact of a higher comparison base are expected to moderate contract price increases to 13–18% QoQ.　　Notably, the ZDNet report says Samsung’s DRAM ASP has risen faster than SK hynix’s. Industry observers attribute the stronger growth to Samsung’s larger share of commodity DRAM, where prices are more volatile, as well as its more aggressive pricing strategy.　　The report also notes that Samsung’s DRAM ASP increased by more than 90% quarter over quarter in the first quarter, with second-quarter growth estimated at 50% to 60%. The company is now targeting another increase of around 20% in the third quarter. By comparison, SK hynix, whose product mix has a higher proportion of HBM, is expected to see a smaller ASP increase.　　Long-Term Pricing Outlook　　The ZDNet report adds that DRAM prices are expected to remain relatively stable going forward. While the pace of price increases is likely to moderate, a growing share of shipments is being secured under long-term supply agreements (LTAs) with key customers.　　Micron disclosed during its earnings release late last month that it had signed 16 LTAs with customers, the report notes. Such agreements reflect customers’ expectations that memory supply will remain tight over the medium to long term. The expansion of LTAs with price floors, together with HBM price renegotiations, should help prevent a sharp downturn in the DRAM market next year, as ZDNet points out.　　The trend toward LTAs has also extended into the automotive sector. Reuters recently reported that Micron signed a long-term memory supply agreement with General Motors, highlighting how customers are increasingly locking in supply amid continued tight market conditions.

Key word：

Samsung

Release time：2026-07-06 13:04 reading：189 Continue reading>>

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SK hynix Unveils KRW 100T Cheongju Investment, Including KRW 80T NAND Fab Set for 1H29 Operations

　　SK hynix has unveiled a major new investment plan. According to ZDNet, President and CEO Kwak Noh-Jung announced at the National Briefing on the Vision for Advanced Industry Development in the Chungcheong Region on July 2 that the company will invest KRW 100 trillion in Cheongju. The plan allocates KRW 80 trillion to the M17 NAND fabrication plant and KRW 20 trillion to P&T7, SK hynix’s advanced packaging facility.　　Construction of the new M17 fab is set to begin in 2027, with operations targeted to commence in the first half of 2029, according to Kwak. P&T7, meanwhile, is scheduled for completion by the end of 2027 and will serve as SK hynix’s advanced packaging hub, the report adds.　　Kwak said the growing adoption of agentic AI and physical AI is broadening NAND flash applications, making further capacity expansion necessary, the report notes.　　The report further notes that SK Group plans to build a 1-gigawatt (GW) AI data center in the Chungcheong region to create synergies between semiconductor manufacturing and AI computing. The group had previously announced plans to establish 15 GW of AI data center capacity across South Korea.　　Samsung Unveils KRW 140 Trillion Investment Plan　　Meanwhile, Samsung also announced KRW 140 trillion in investments at the same event, Newsis reports. The investment plan includes KRW 67 trillion to expand Samsung Display’s advanced OLED production lines in Asan, KRW 56 trillion for Samsung Electronics’ HBM fabs in Onyang and Cheonan, KRW 9 trillion for Samsung SDI to build a next-generation battery mother line in Cheonan, and KRW 8 trillion for Samsung Electro-Mechanics to establish high-performance AI server package substrate production in Sejong.

Key word：

SK hynix

Release time：2026-07-03 16:03 reading：269 Continue reading>>

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ASE Reportedly Raises Advanced Packaging Quotes by More Than 20% in Latest AI-Driven Price Hike

　　AI-driven semiconductor demand is reportedly fueling another round of price increases across the OSAT industry. According to MoneyDJ, citing industry sources, ASE, the world’s leading outsourced semiconductor assembly and test (OSAT) provider, has raised its packaging quotes by more than 20%, driven by higher raw material costs and higher long-term investment costs.　　The latest price increases cover advanced packaging technologies such as Chip-on-Wafer-on-Substrate (CoWoS) and Fan-Out Chip on Substrate (FoCoS), with major U.S. customers among those affected, the report says.　　ASE declined to comment on the market speculation, the report adds.　　The report indicates that ASE has become a key beneficiary of the AI-driven advanced packaging boom. With TSMC’s CoWoS capacity still supply-constrained and outsourcing continuing to increase, the company is seeing stronger demand for its on-substrate (oS) packaging and chip probing (CP) services.　　Meanwhile, utilization rates across the OSAT industry remain near full capacity, with both leading and smaller providers actively expanding capacity to meet rising demand, the report notes.　　AI Fuels OSAT Investment and Capacity Expansion　　Commenting on the pricing strategy, ASE COO Tien Wu said the increases reflect two key factors: higher raw material costs and growing capital investment requirements, according to MoneyDJ.　　Those long-term investments are being fueled by AI. According to Liberty Times, Wu said AI has become the key driver behind ASE’s capacity expansion plans. As AI adoption extends beyond data centers into physical AI applications such as automotive electronics and humanoid robots, he described the trend as a long-term structural shift and said the ASE Group is “going all out” to expand capacity.　　To support future demand, Wu estimates that ASE and its subsidiary SPIL have around 15 new factory projects underway this year to prepare for demand expected from 2029 to 2030 and beyond, according to Liberty Times. ASE increased capital expenditures to US$5.3 billion in 2025 and further raised its 2026 capex to US$8.5 billion, with additional increases remaining possible.　　The aggressive capacity expansion reflects a broader industry trend. As noted by Economic Daily News, competition in AI has expanded beyond leading-edge processes, making backend packaging, testing, and assembly increasingly critical to chip performance, yields, and time-to-market. As a result, major OSAT providers are accelerating investments in technologies such as 2.5D/3D packaging, chiplets, HBM integration, and panel-level packaging, further positioning the sector as a key capacity bottleneck in the AI semiconductor supply chain.

Key word：

ASE

Release time：2026-07-02 15:57 reading：268 Continue reading>>

Trade news

Samsung Reportedly Restarts 1.4nm Push, Targets 2029 Mass Production to Close Gap with TSMC, Intel

　　As Intel and TSMC both target 1.4nm mass production around 2028-29, Samsung—after reportedly delaying its own roadmap—is now re-entering the race. According to The Bell, the company has resumed efforts to commercialize its 1.4nm (SF1.4) foundry process, with mass production now slated for 2029, placing it slightly behind its leading rivals.　　Samsung is also understood to have recently requested early development of process equipment from domestic and overseas partners. As noted by the report, it has recently shared its 1.4nm process roadmap with major semiconductor equipment makers, including Applied Materials and Lam Research.　　Notably, the report, citing industry sources, points out that Samsung Electronics has already installed ASML’s next-generation High-NA extreme ultraviolet (EUV) lithography equipment at its NRD-K facility. The High-NA EUV tools are understood to be applied to select layers starting from the 1.4nm process, the report explains.　　Why Samsung Delayed 1.4nm Plans　　The Bell adds that the original 2027 target has been pushed back to 2029, as Samsung redirects focus toward strengthening its 2nm (SF2) and derivative SF2P processes, signaling a shift toward yield stabilization and process optimization over aggressive node advancement.　　This strategic pivot is also reflected at the product level. A previous Global Economic News report suggested that Samsung has shifted the manufacturing process for its next-generation flagship smartphone processor, the Exynos 2800, from the originally planned 1.4nm node to an advanced version of its 2nm process.　　A Closer Look at 1.4nm Plans for Intel, TSMC　　Samsung Electronics’ renewed push into its 1.4nm process is drawing attention over whether it can narrow the technology gap with rivals such as TSMC and Intel. According to Economic Daily News, TSMC is targeting 1.4nm pilot production as early as 3Q27, with mass production planned for 2H28.　　However, Tom’s Hardware notes that TSMC is expected to skip ASML’s High-NA EUV tools through 2029, meaning its 1.4nm node would proceed without the advanced system being adopted by Intel and Samsung.　　For Intel, Reuters reports that its 18A-P process has already entered pilot production, with the company reportedly targeting 14A risk production in 2028, followed by high-volume manufacturing in 2029.

Key word：

Samsung

Release time：2026-07-01 11:39 reading：344 Continue reading>>

Trade news

Korea’s High-Purity CO₂ Inventory Reportedly Falls Below One Month; Samsung, SK hynix Under Pressure

　　Recent geopolitical tensions have created another potential bottleneck for Korea’s semiconductor supply chain. The supply of high-purity carbon dioxide (CO₂) used in advanced semiconductor manufacturing has reportedly tightened. According to The Elec, industry sources say total inventory across the supply chain has recently fallen below one month’s supply. Under normal conditions, semiconductor manufacturers and gas suppliers each maintain about two weeks of inventory, equivalent to roughly one month’s supply in total.　　Samsung Electronics is estimated to consume approximately 1,800–2,000 metric tons of high-purity CO₂ each month, while SK hynix uses roughly 600–700 metric tons, the report says.　　The report notes that production at Samsung Electronics and SK hynix has not yet been affected. However, shrinking inventory buffers have prompted both companies to step up procurement efforts, although additional supply remains difficult to secure even at higher prices.　　Still, according to Mydrivers, sources say that if supply tightness persists, Samsung and SK hynix’s advanced DRAM and NAND production will face pressure, making price increases inevitable.　　Why High-Purity CO₂ Matters for Chip Manufacturing　　High-purity CO₂ plays a key role in supercritical semiconductor cleaning processes. The Elec notes that when CO₂ exceeds its critical temperature and pressure, it enters a supercritical state that combines the properties of liquids and gases. This enables it to effectively dissolve wafer residues while penetrating deep into fine semiconductor patterns to remove contaminants, making the technology well suited for advanced semiconductor manufacturing.　　The availability of high-purity CO₂ is closely tied to the supply of its upstream feedstock. As The Elec notes, CO₂ feedstock is recovered as a byproduct of oil refining, petrochemical production, and hydrogen manufacturing. Instability in crude oil supplies caused by tensions in the Middle East, coupled with lower operating rates at South Korea’s petrochemical plants, has significantly reduced the availability of CO₂ feedstock.　　The report adds that liquefied CO₂ prices have risen by roughly 20% since the beginning of the year, with industry sources expecting supply tightness to persist through the end of 2026. South Korea’s major suppliers of high-purity CO₂ include Taekyung Chemical, Sundo Chemical, Dongkwang Chemical, and SK Airplus, with Taekyung Chemical recognized as the country’s leading supplier.　　An industry expert cited by The Elec said geopolitical risks stemming from the Middle East are once again disrupting semiconductor material supplies, following earlier disruptions involving helium, anhydrous hydrogen fluoride, and propylene glycol monomethyl ether acetate (PGMEA).

Key word：

Korea’s High-Purity CO₂

Release time：2026-06-30 10:59 reading：345 Continue reading>>

Trade news

ROHM Launches AG16xFNxx Series MOSFETs for Automotive 48V Power Supply Systems

　　ROHM has developed the “AG16xFNxx Series,” a lineup of 80V power MOSFETs designed for 48V power supply systems, which are becoming increasingly common in automotive applications.　　In the automotive sector, power demand is increasing, particularly in high-end vehicle models. 48V power supply systems are gaining attention as a highly efficient alternative to conventional 12V power supply systems. With widespread adoption expected around 2030, there is a growing need for 80V power MOSFETs that can achieve even lower power losses than standard 100V devices.　　ROHM’s new products are expected to enable downsizing compared to standard automotive MOSFET packages such as the TO-252 (6.6 × 10.0mm) by adopting the HPLF5060 (4.9 × 6.0mm) and DFN3333 (3.3 × 3.3mm) packages.　　The HPLF5060 features Gull-Wing Leads, while the DFN3333 features Wettable Flank Technology, contributing to improved reliability on PCBs (Printed Circuit Boards). Furthermore, by adopting Copper Clip Junction Technology to enhance heat dissipation, these devices are capable of handling high currents. All models comply with the automotive reliability standard AEC-Q101, ensuring high reliability.　　Mass production of new products began in April 2026 for the AG160FNS4FRA (HPLF5060) and the AG166FNH7FRA (DFN3333) (sample price: $3.5/unit, excluding tax). Online sales have also started, and the products are also available for online purchase through online distributors such as DigiKey and Farnell.　　The product lineup of these packages will be further expanded in the near future. In addition, development of TOLG (TO-Leaded with Gullwing, 9.9 × 11.7mm) packaged products has begun, with continued expansion of the lineup of high-power, high-reliability 80V MOSFETs.　　Application ExamplesAutomotive 48V systems: Main inverter control circuits, electric motors, electric water pumps, etc　　EcoMOS™ BrandEcoMOS™ is ROHM's brand of silicon power MOSFETs designed for energy-efficient applications in the power device sector.　　Widely utilized in applications such as home appliances, industrial equipment, and automotive systems, EcoMOS™ provides a diverse lineup that enables product selection based on key parameters such as noise performance and switching characteristics to meet specific requirements.　　・EcoMOS™ is a trademark or registered trademark of ROHM Co., Ltd.　　TerminologyGull-Wing Leads　　A terminal structure that spreads outwards from both sides of the package. It provides higher mounting reliability. It is called “Gull-Wing” because its appearance resembles the wing of a seagull.　　Wettable Flank Technology　　A technology for plating the sides of the lead frame on bottom electrode packages such as QFN and DFN to improve mounting reliability.　　Copper Clip Junction Technology　　A technology that uses copper clips (flat metal bridges) to connect chips and lead frames directly, replacing the conventional wire bonding method.

Key word：

ROHM

Release time：2026-06-29 11:20 reading：292 Continue reading>>

model	brand	Quote
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor
MC33074DR2G	onsemi
BD71847AMWV-E2	ROHM Semiconductor

model	brand	To snap up
STM32F429IGT6	STMicroelectronics
ESR03EZPJ151	ROHM Semiconductor
IPZ40N04S5L4R8ATMA1	Infineon Technologies
TPS63050YFFR	Texas Instruments
BU33JA2MNVX-CTL	ROHM Semiconductor
BP3621	ROHM Semiconductor

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