ASML Continues to Ramp <span style='color:red'>EU</span>V Shipments
  Dutch microlithography system vendor ASML said it on track to grow sales by at least 25 percent this year after a strong third quarter characterized by strong demand for 193-nm tools and the continued ramp up deliveries for next-generation extreme ultraviolet (EUV) systems.  ASML (Veldhoven, the Netherlands) said it shipped three Twinscan NXE:3400B EUV tools in the third quarter, raising the total for the year so far too six. NXE:3400B is ASML's second-generation EUV production tool intended for volume production at the 7nm and 5nm nodes.  ASML said it currently has a backlog of 23 EUV systems, down from a backlog of 27 systems at the end of the second quarter. The company said it also demonstrated during the second quarter that its EUV pellicle — which protects the photomask from particles during exposure — is capable of withstanding 250 watts of EUV power, another important milestone in the development of EUV.  Among other third quarter highlights, ASML also announced the shipment of the first product jointly developed with the engineering team of Hermes Microvision, the Taiwanese pattern verification system vendor it bought last year for about $3.1 billion. The product, ePfm5, is a pattern fidelity metrology tool that offers customers enhanced capabilities for detecting patterning defects, ASML said.  ASML reported third quarter sales of about 2.45 billion euros (about $2.9 billion), up 17 percent compared with the second quarter. The firm reported a third quarter net income of 557 million euros (about $657 million), up 20 percent from the second quarter.  For the fourth quarter, ASML said it expects sales to slide to about 2.1 billion euros (about $2.48 billion). The firm expects its fourth quarter gross margin to be about 44 percent, up from 42.9 percent in the third quarter.  With the strong third quarter sales and fourth quarter guidance, ASML affirmed its earlier guidance that its 2017 sales will be up at least 25 percent compared to 2016.  "Our current view is that the positive business environment that we are seeing today will continue in 2018, supported by our strong backlog of 5.7 billion euros [$6.7 bill], which is driven by all product categories," said ASML President and CEO, Peter Wennink, in a press statement.
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Release time:2017-10-20 00:00 reading:1277 Continue reading>>
 Intel May Sit Out Race to <span style='color:red'>EU</span>V
  A race is on to qualify advanced semiconductor process technologies using extreme ultraviolet (EUV) lithography, but Intel is said to be sitting on the sidelines.  ASML reported in July a backlog of 21 orders for the EUV systems which cost as much as $150 million each. The company is expected to take through 2019 to fill the orders. It announced in March its NXE:3400B as its first production-ready system.  “The biggest problem is getting more lenses, Zeiss doesn’t have capacity to supply more,” said G. Dan Hutcheson, chief executive of market watcher VLSI Research. Hutcheson expects eight or nine systems will be delivered this year.  After years of achingly slow development, the systems are now approaching production worthiness. In addition, demand from leading-edge chip makers has accelerated just as foundries realized they could use the systems more extensively at introduction than once believed.  “Everyone talked about using EUV on one or two mask layers coming in, but now its five, six or seven mask layers,” said Hutcheson.  He forecasts $1.482 billion will be spent on EUV this year, up from $1.036 billion last year and rising to $3 billion in 2019. Spending is “already a third of the level of the 193 equivalant,” he said of the comparison traditional argon fluoride steppers.  Samsung and TSMC are racing to announce some level of manufacturing with EUV next year. But Intel is said not to be ordering materials needed for EUV at the same rate, according to one source that asked not to be named.  The dynamic makes sense because Samsung and TSMC must compete for high-volume leading-edge business from customers such as Apple and Qualcomm, while Intel’s fledgling foundry operation does not.  Hutcheson and other sources contacted said they were not aware of any delay implementing EUV at Intel. The x86 giant itself declined to comment on its EUV timeline.  “We are committed to bringing EUV into production as soon as the technology is ready at an effective cost. The road to EUV lithography production is a long one. While there has been great progress, much work remains. It’s important that our industry partners and suppliers are engaged and pushing as hard as we are to meet the requirements for high volume manufacturing,” an Intel spokesman said via email.  In June Globalfoundries CTO Gary Patton said engineers still have to resolve several issues with EUV. Most importantly, defects in masks need to be reduced and protective pellicles for EUV wafers still need to be designed, he said.  “Intel’s probably not going to be the first to implement EUV, but they [initially] bought more EUV tools than anyone…[and] Intel will do a lot more pre-qualifications because they want the highest performing chips,” said Hutcheson. “I’m sure next year some people will announce manufacturing with EUV, but the ramp will really be in 2019,” he added.  “It’s just a balancing act in my opinion,” said Vivek Bakshi, who is updating a book he wrote on EUV and planning a workshop in November on the follow-on EUV system expected for use at 5-3 nm nodes.  “It doesn’t matter whether one is a year or six months earlier than another. If you look at the time it’s taken to get EUV developed, the starting time for production is in the noise. Over the next two to three years everyone at the leading edge will use it,” said Bakshi, noting Intel was among the first to start EUV development in the late 1990’s.  Intel continues to invest in capital equipment at traditional levels, with $12 billion in spending projected this year compared to $17 billion for Samsung and $10 billion for TSMC, said Hutcheson. Last year, Intel spent $9.5 billion, while Samsung and TSMC were at $11.5 and $10.2 billion, respectively. Globalfoundries is a distant fourth at $2.5-$2.8 billion a year over the last two years.  Samsung has been the biggest capex spender over the last few years as it ramps 3D NAND flash production, said Hutcheson. Likewise, a significant portion of Intel’s capex is going to bring up 3D NAND in Dalian, China and 3D XPoint memories in Lehi, Utah with Micron.  In the third quarter, there was a shortage of capacity in DRAM and NAND segments as well as among integrated device makers like Intel, Hutcheson said. “We think that will continue through this quarter,” he said.  “Intel is running flat out from what we see, while Samsung’s 3D NAND expansion is huge,” he added.
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Release time:2017-10-11 00:00 reading:1291 Continue reading>>
Globalfoundries Reportedly Asks <span style='color:red'>EU</span> to Probe TSMC
Release time:2017-09-22 00:00 reading:1391 Continue reading>>
Samsung Says <span style='color:red'>EU</span>V on Schedule for 2018
  South Korea's Samsung Electronics Co. Ltd. confirmed that it continues to expect to put extreme ultraviolet (EUV) lithography into initial production with its 7nm Low Power Plus (LPP) process in the second half of next year.  Samsung (Seoul) also announced the addition of an 11nm LPP process utilizing FinFET technology to its process technology offerings, saying it would deliver up to 15 percent higher performance and up to 10 percent reduction in chip area compared to its 14nm LPP process while consuming the same amount of power.  EUV, the long-heralded successor to 193nm lithography that has been delayed numerous times over the past decade, finally appears to be poised for prime time with leading edge chip makers Intel, TSMC, Samsung and Globalfoundries all targeting production deployment over the next 18 months.  The results of a survey of 75 semiconductor luminaries released Monday (Sept. 11) indicated that 75 percent now believe that EUV will be adopted in high-volume manufacturing before 2021. Just 1 percent said EUV will never be embraced, down from 6 percent last year and a whopping 35 percent in 2014.  Samsung said it has processed close to 200,000 wafers with EUV lithography technology since 2014 and has recently seen visible improvement with EUV technology, such as achieving  80 percent yield for 256 Mb SRAM.  Samsung said Monday that it expects that its 10nm FinFET process for mobile smartphone processors and its 11nm LPP process would bring differentiation and value to mid- and high-end phones.
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Release time:2017-09-13 00:00 reading:1315 Continue reading>>
Chip Execs More Bullish on <span style='color:red'>EU</span>V
  Chip executives are increasingly optimistic the industry will adopt extreme ultraviolet lithography and multibeam mask writers, according to a pair of surveys announced today. The new systems will help drive advances at a time when it’s becoming increasingly complex and expensive to make leading-edge devices.  Seventy-five percent of a survey of 75 semiconductor luminaries said they expect EUV will be adopted in high volume manufacturing before 2021. Only 1 percent said EUV will never be embraced, down from 6 percent last year and a whopping 35 percent in 2014.  “There’s no question in my mind,” EUV will be adopted starting with 7nm+ processes in the next few years, said Aki Fujimura, an industry veteran and spokesman for the eBeam Initiative, a trade group that conducted the survey over the summer.  Intel, Samsung and TSMC made multi-billion-dollar investments in EUV developer ASML which in turn bought light-source maker Cymer, driving the complex and expensive technology forward. “Over the last couple years, the problem got bad enough with 7 and 5nm that everyone finally said we got to make this work or the entire industry’s in trouble,” said Fujimura, who is chief executive of D2S, a maker of systems that use GPUs to accelerate mask defect repair.  The shift won’t be easy. Chip makers are expected to launch 7nm processes with existing immersion steppers, then migrate some steps to EUV later to reduce the need for multi-patterning.  “EUV is so novel and requires so much investment in the machine and ecosystem to support it that you can’t have a stepwise introduction. You have to introduce it more gradually than that …[and not] ask EUV to do its best right off the bat,” said Fujimura who is on his third startup after a career in EDA that started in 1979 and included two tours at Cadence Design Systems.  Over the past 12 months, mask makers created 1,041 EUV masks, up from 382 a year ago. EUV mask yields were only 64.3 percent, compared to 94.8 percent for all 462,792 masks exposed in the period, according to a separate survey of ten top mask makers.  “I attribute [the low figure] to startup yields…One might say it’s surprising it’s as high as 64.3 percent,” he said.  The chip execs were also bullish that multi-beam mask writers will see use in high volume manufacturing by the end of 2019, about a year later than they predicted in a 2016 survey. This year’s survey suggested existing variable shaped beam (VSB) mask writers will see longer use than expected.  The shift comes a time when mask sets and thus costs are still rising dramatically at leading-edge nodes. However, the survey of mask makers reported write times are generally stable.  Mask write times are “under control” in part because the latest VSB systems deliver up to 1,200 Amps/cm2, Fujimura said. However increasing data sets and defects are stretching out mask turnaround times for finer nodes. “Mask cost is increasing per critical layer and the number of masks is getting very high,” he said.  Indeed, respondents said 7-10nm nodes have 76 masks on average with a maximum of 112 masks reported by one company. That’s up from an average of 50 masks for the last planar node at 20nm and 25 masks at 130nm.  “More than 100 is clearly ridiculous,” he said. “We’ll see what happens with EUV” which requires fewer masks than immersion steppers, but the EUV masks are more complex and thus expensive to make, he added.  Meanwhile mask turnaround time for 7-10nm processes has stretched out to an average of 12 days, the survey said. That’s in part because it now takes about 21 hours on average for data preparation.  In addition, mask process correction (MPC) is now becoming a routine requirement as chips approach 7nm. The step takes an additional 21 hours on average, according to the survey. “MPC is exploding. Adding this extra step introduces extra run time,” Fujimura said.
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Release time:2017-09-12 00:00 reading:1412 Continue reading>>
Intel Wins Appeal on <span style='color:red'>EU</span> Antitrust Fine
  Back in 2009, European antitrust regulators handed Intel a very bitter pill — a $1.3 billion-dollar fine for incentivizing computer makers to choose their devices over competitor AMD's with what the European Commission felt were inappropriate rebates that could be interpreted as bribes to the companies involved. Intel has been aggressively fighting that ruling ever since.  A European Union appeals court on Wednesday (Sept. 6) — while not directly exonerating the company — dealt a major blow to the case by referring the decision back to a lower court and asking it to re-evaluate the fine — a strong signal that winds have shifted in Intel's favor.  An earlier appeals court ruling in the summer of 2014 had upheld the original decision. That ruling was seen then as a rebuke to Intel and a sign to the community that no company is above the rulings of the court. This tossing back to a lower court of the case has completely reversed the momentum previously created, throwing the outcome of the case back into uncertainty.  "The lengthy appeals process took a major step in Intel’s favor today, with the ruling that the General Court should have considered whether Intel’s pricing practices were capable of harming competition," wrote Steve Rogers, Intel executive vice president and general counsel, in a blog post on the company's website. "The court sent the case back to the General Court for reassessment in light of its holding."  Not only has this move made the final status of the now $1.5 billion-plus (exchange rates and inflation) fine uncertain, it also emboldens other companies now sparring with the EU in trade court, chief among them Google, who was recently fined around $2.5 billion dollars for antitrust activity stemming from its dominance of the search industry. Intel’s success, if nothing else, gives other entities hope to evade Brussel’s regulatory scalpel.
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Release time:2017-09-08 00:00 reading:1216 Continue reading>>
<span style='color:red'>EU</span> Regulators Again Halt Qualcomm-NXP Investigation
  European Union regulators have for a second time put the brakes on their investigation into the proposed $38 billion acquisition of NXP Semiconductors by Qualcomm.  The European Commission said in a posting on its website that the investigation was suspended on Aug. 17. The Reuters news service reported Wednesday (Sept. 6) that Qualcomm and NXP failed to supply regulators with key information about the proposed merger and that the investigation would resume after the information was received.  Qualcomm (San Diego) announced last October the deal, valued at about $38 billion, to acquire NXP (Eindhoven, the Netherlands). The EU launched an investigation into the proposed acquisition in June, citing concerns into the merged entity's position in NFC, mobile devices and vehicle-to-vehicle and vehicle-to-infrastructure technology.  The suspension marks the second time that EC regulators have paused the investigation to await documents from the firms. They also suspended the acquisition in June, shortly after it began.  The deadline for regulators to conclude their investigation is Oct. 17. According to the Reuters report, the EC will specify a new target date for completion of the investigation once they receive the requested information.  Analysts do not generally believe that there is much danger that the acquisition will be nixed by regulators. The two companies' product portfolios generally speaking have very little overlap, and the deal has already received a green light from regulators in the U.S. and elsewhere.  Neither the EC website or the Reuters report specified what information the regulators are waiting for. Both Qualcomm and NXP did not immediately respond to a request for comment on the issue by EE Times.
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Release time:2017-09-07 00:00 reading:1152 Continue reading>>
Google Fellow: Neural Nets Need Optimized Hardware
  If you aren't currently considering how to use deep neural networks to solve your problems, you almost certainly should be, according to Jeff Dean, a Google senior fellow and leader of the deep learning artificial intelligence research project known as Google Brain.  In a keynote address at the Hot Chips conference here Tuesday (Aug. 22), Dean outlined how deep neural nets are dramatically reshaping computational devices and making significant strides in speech, vision, search, robotics and healthcare, among other areas. He said hardware systems optimized for performing a small handful of specific operations that make up the vast majority of machine learning models would create more powerful neural networks.  "Building specialized computers for the properties that neural nets have makes a lot of sense," Dean said. "If you can produce a system that is really good at doing very specific [accelerated low-precision linear algebra] operations, that's what we want."  Of the 14 Grand Challenges for Engineering in the 21st Century identified by the National Academy of Engineering in 2008, Dean believes that neural networks can play an integral role in solving five — including restoring and improving urban architecture, advancing health informatics engineering better medicines and reverse engineering the human brain. But Dean said neural networks offer the greatest potential for helping to solve the final challenge on the NAE's list: engineering the tools for scientific discovery.  "People have woken up to the idea that we need more computational power for a lot of these problems," Dean said.  Google recently began giving to customers and researchers access to the second-generation of its TensorFlow processing unit (TPU) machine-learning ASIC through a cloud service. A custom accelerator board featuring four of the second-generation devices boasts 180 teraflops of computation and 64 GB of High Bandwidth Memory (HBM).  Dean said the devices is designed to be connected together into larger configurations — a "TPU pod" featuring 64 second-generation TPUs, cable of 11.5 petaflops and offering 4 terabytes of HBM memory. He added that Google is making available 1,000 Cloud TPUs for free to top researchers who are committed to open machine learning research.  "We are pretty excited about the possibilities of the pod for solving bigger problems," Dean said.  In 2015, Google released its TensorFlow software library for machine learning to open source with a goal of establishing a common platform for expressing machine learning ideas and systems. Dean showed a chart demonstrating that TensorFlow in just over a year and a half has become far more popular than other libraries with similar uses.  "It's been pretty rewarding to have this rather large community now crop up," Dean said.  The rise of neural networks — which has accelerated greatly over the past five years — has been made possible by tremendous advances in compute power over the past 20 years, Dean said. He added that he actually wrote a thesis about neural networks in 1990. He believed at the time that neural networks were not far off from being viable, needing only about 60 times more compute power than was available then.  "It turned out that what we really needed was about 1 million times more compute power, not 60," Dean said.
Release time:2017-08-24 00:00 reading:1327 Continue reading>>
Semi sales through European distributors continue to boom
  Demand for semiconductors from European companies showed no signs of slowing during the second quarter of 2017, according to distribution association DMASS. In its latest report, the organisation noted record semiconductor sales of €2.19billion, 17.3% higher than in the corresponding quarter of 2016.  Georg Steinberger, DMASS’ chairman, noted: “The dynamic growth over the last nine months was unprecedented. Significant allocations in several product areas make it difficult to predict the rest of the year, but it would be safe to assume that double-digit growth will continue through 2017.  Germany remains the biggest single market, with demand growing by 13.7% to €653million during the quarter. Meanwhile, sales into the UK and Ireland rose by 9.6% to €154m.  Analogue ICs – the largest product group reported by DMASS – saw sales grow by 16.7% to €656m, whilst sales of micros rose by 15.6% to €443 . Meanwhile, programmable logic sales increased by 27.1% to €155m and sales of memories by 27.9% to €183m.  Steinberger commented: “Programmable Logic is experiencing higher growth, despite channel shifts from distribution to direct, but this could be seasonal. However, even without these very particular growth spikes, the distribution market in Europe shows healthy double-digit growth.”  Despite the strong performance in the first half of 2017, DMASS doesn’t have a clear picture for the remainder of the year. "Looking forward remains difficult,” Steinberger concluded, “but DMASS totals of €8bn – an all-time record – are in range for the full year. What is surprising is that growth comes from almost all industry segments, driven by a higher electronics content across many applications.”
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Release time:2017-08-18 00:00 reading:1162 Continue reading>>
Neural Accelerator Battle Begins
  The embedded market for neural network accelerators is heating up, with more systems — ranging from smart speakers and drones to light bulbs — poised to run neural networks locally instead of going back to the cloud for computation.  In an interview with EE Times, Remi El-Ouazzane, vice president and general manager of Movidius, defined the growing trend as “a race for making things smart and autonomous.”  Movidius, an Intel company, launched Thursday (July 20) a self-contained AI accelerator in the form of a USB stick. Called Movidius Neural Compute Stick, it is designed to plug simply into Raspberry Pi or X86 PCs. The Neural Compute Stick makes it easier for university researchers, independent software developers and tinkerers to compile, tune and accelerate deep learning applications for embedded systems, said El-Ouazzane.  Movidius, acquired by Intel last fall and now a part of Intel’s New Technology Group, developed Myriad 2 VPU, the industry’s first always-on vision processor. El-Ouazzane said his ultimate goal in rolling out the stick is to make Movidius VPU “a reference architecture” for neural networks running at the edge.  While the goal is ambitious, industry analysts were quick to point out that Movidius’ Myriad 2 VPU certainly isn’t the only device for running neural networks at the edge in embedded systems.  Plethora’s neural accelerators  Jim McGregor, principal analyst at Tirias Research, said “Technically, you could or would use any board that has a processing element and is intended to run a model.” He explained, “Machine learning/AI models already run on a wide variety of processors and SoCs, especially in the mobile segment.”  A case in point, said McGregor, is Qualcomm-enabled image recognition on the Snapdragon family, beginning with the 820 using a model developed by Qualcomm. “The Snapdragon is essentially the inference engine,” McGregor said.  Processing solutions that feature parallel processing elements like GPUs, DSPs and FPGAs are well suited as inference engines. Many of the customized silicon solutions under development are using DSPs or FPGAs embedded into an SoC, explained McGregor.  Linley Gwennap, principal analyst at the Linley Group, agreed. In a recent editorial published in Microprocessor Report June 19, Gwennap wrote that Qualcomm, Apple and Intel (Movidius) are all “creating a new product category: neural accelerators.”  Explaining that the demand for these client-based accelerators is coming from self-driving cars, which demand as little latency as possible, Gwennap noted in his editorial the new technology that handles the processing locally “will trickle down to less expensive applications.” He predicted, “In consumer devices, a small neural accelerator is likely to be a block in the SoC, much like a graphics or image processor. Several intellectual-property (IP) vendors offer such accelerators, minimizing the cost of the extra hardware.”
Release time:2017-07-24 00:00 reading:989 Continue reading>>

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