TSMC’s Roadmap Full, But Thin

Continuing to move fast in multiple directions at once, TSMC announced that it is in volume production with a 7-nm process and will have a version using extreme ultraviolet (EUV) lithography ramping early next year. In addition, it gave its first timeline for a 5-nm node and announced a half-dozen new packaging options.

Meanwhile, the foundry is pushing power consumption and leakage down on more mainstream 22-/12-nm nodes, advancing a laundry list of specialty processes and rolling out an alphabet soup of embedded memories. At the same time, it is exploring future transistor structures and materials.

Overall, the Taiwanese giant expects to make 12 million wafers this year with R&D and capex spending both on the rise. It has even started production of 16-nm FinFET chips in Nanjing, a big first for China.

The only bad news is that the advantages with the new process nodes are getting thinner. The new normal for performance gains and power reductions generally fall in a 10% to 20% range, a reality that makes the new packaging and specialty processes increasingly important.

TSMC is in volume production of 7-nm chips today with more than 50 tapeouts expected this year. It’s making CPUs, GPUs, AI accelerators, cryptocurrency mining ASICs, networking, gaming, 5G, and automotive chips.

The node delivers 35% more speed or uses 65% less power and sports a 3x gain in routed gate density. By contrast, the N7+ node with EUV will only deliver 20% more density, 10% less power, and apparently no speed gains — and those advances require use of new standard cells.

TSMC has validated in silicon what it calls foundation IP for N7+. However, several key blocks will not be ready until late this year or early next year, including 28–112G serdes, embedded FPGAs, HBM2, and DDR5 interfaces.

Expect 10% to 20% more effort laying out IP for the EUV process, said Cliff Hou, vice president of R&D for design and technology platforms. “We developed a utility to migrate IP with incremental effort.”

Fully certified EDA flows for N7+ will be ready by August. Meanwhile, yields of a test 256-Mbit SRAM at N7+ are as good as yields were for the early 7-nm node, he said.

Looking ahead, TSMC aims to start risk production of a 5-nm node in the first half of 2019, focusing on mobile and high-performance computing chips.

Compared to the initial 7 nm without EUV, the 5-nm node promises a 1.8x greater density than 7 nm. However, it is only expected to reduce power by up to 20% or raise speeds by about 15%, perhaps 25% using Extremely Low Threshold Voltage (ELTV), details of which TSMC has not yet provided.

“Without EUV, they can’t deliver the same scaling advantage as past nodes,” said Mike Demler, an analyst with the Linley Group. “If you look at N7+, they claim an additional 20% scaling over N7. So EUV is required to get closer to traditional Moore’s Law scaling. Their N5–N7 scaling just gets worse.”

TSMC clearly has a bead on high-volume manufacturing for EUV early next year. It got systems to sustain production at 250 W for a couple of weeks in April and aims to hit 300 W next year, a power level needed for volume throughput.

With average daily power levels at 145 W, the foundry has a ways to go, but “throughput is on track to meet production needs,” said Y.J. Mii, vice president of R&D for technology development.

Besides “significant progress on power and throughput,” Mii reported that resist dosage is declining toward the foundry’s 1Q19 production goal, though it’s still about a third too high. The protective pellicle transmits 83% of EUV light and should hit 90% next year.

EUV continues to provide much better uniformity of critical dimensions than immersion steppers, said Mii, showing several examples. The foundry expects to use EUV on multiple layers in both N7+ and 5-nm nodes and is aggressively installing NXE3400 systems from ASML.

It appears that TSMC’s EUV plan is within six months of the production schedule of Samsung, which has said that it will be in production this year. The South Korean giant plans its own event later this month, where it will provide an update on its progress.

The gap is not likely enough to get large-volume customers such as Apple or Qualcomm to switch suppliers. In the long term, a lead of a few months will be insignificant, said G. Dan Hutcheson, chief executive of market watcher VLSI Research.

Meanwhile, TSMC’s 5-nm node is still embryonic with a version 0.5 EDA flow targeted for June release and a v0.5 design kit in July. Many IP blocks won’t be validated until next year, including PCIe Gen 4, DDR4, and USB 3.1 interfaces.

By the end of 2019, the foundry aims to triple to 1.1 million wafers/year its production on 10-/7-nm nodes. It’s latest fab complex 18 is under construction in Taiwan now and aims to start 5-nm production in 2020.

Now that TSMC has established its 2.5-D CoWoS package in GPUs and other processors and its wafer-level fan-out InFO in smartphone chips, it is expanding both offerings and adding others.

CoWoS chips will have options for silicon interposers up to twice a reticle’s size, apparently stitched in the field, starting early next year. Versions with 130-micron bump pitch will be qualified this year.

The InFO technique is getting four cousins. Info-MS, for memory substrate, packs an SoC and HBM on a 1x reticle substrate with a 2 x 2-micron redistribution layer and will be qualified in September.

InFO-oS has a backside RDL pitch better matched to DRAM and is ready now. A multi-stacking option called MUST puts one or two chips on top of another larger one linked through an interposer at the base of the stack.

Finally, InFO-AIP stands for antenna-in-package, sporting a 10% smaller form factor and 40% higher gain. It targets designs such as front-end modules for 5G basebands.

“InFO is an important platform,” said Jan Vardaman, a veteran packaging analyst and president of TechSearch International.

“TSMC’s InFO for baseband/modem package in a PoP with memory is very impressive — lower profile, smaller form factor, and better performance. InFO on Substrate is going to be popular because it’s 2-micron lines and spaces will cover a lot of applications.”

But that’s not all. TSMC introduced two wholly new packaging options.

A wafer-on-wafer pack (WoW) directly bonds up to three dice. It was released last week, but users need to ensure that their EDA flows support the bonding technique. It will get EMI support in June.

Finally, the foundry roughly described something that it called system-on-integrated-chips (SoICs) using less than 10-micron interconnects to link two dice, but details are still sketchy for the technique to be released sometime next year. It targets apps from mobile to high-performance computing and can connect dice made in different nodes, suggesting it may be a form of system-in-package.

“It used to be ASE leading the way in packaging, but now I’d say TSMC is,” said one analyst during a break.

The motivations are clear. As the advantages of CMOS scaling diminish, packaging helps deliver performance, in part through faster memory access. In the last few years, TSMC, which runs three back-end production lines, won significant business with Apple in part due to InFO and Xilinx and Nvidia in part with CoWoS.

The new packages “look like the long-promised alternative to the end of Moore’s Law, but pretty expensive and still with lots of issues,” said Demler of Linley Group.

Only about a third of TSMC’s business is at advanced nodes such as 28 nm and beyond. Thus, the foundry discussed advances in a laundry list of specialty processes as well as advances a step or two back from the bleeding edge.

For example, it is developing ultra-low-power and ultra-low-leakage versions of its 22-nm planar and 12-nm FinFET nodes. They will compete with FD-SOI processes ramping at Globalfoundries and Samsung.

The new 22-nm versions use 28-nm design rules and deliver a 10% optical shrink and speed gain or can reduce power 20%. The process and related IP will be ready by the end of the year with target apps including advanced microcontrollers, IoT, and 5G millimeter-wave chips.

The 12-nm versions use FinFETs and more compact cell libraries to deliver about 16% more speed than TSMC’s 16FFC. High-speed serdes are among the few pieces of IP that won’t be ready until next year.

In memories, a 40-nm resistive RAM is now ready as an alternative to flash for IoT chips. It adds just two mask layers and sports 10 years of retention and support for 10,000 cycles.

A 22-nm embedded MRAM will debut this year that’s faster and has longer retention than flash. It targets automotive, mobile, and high-performance designs with good yields on test chips so far.

Separately, TSMC is delivering smaller form factors for MEMS. It expects GaN-on-silicon with 10-V and 650-V driver integration in the fall and 100-V D-HEMT qualified next year for cellular power amps.

In addition, the foundry has qualified EDA flows and IP for its 16FFC process for automotive. It plans to have a 7-nm automotive process ready by the end of the year, though full certification will take until 2Q19.

As icing on the cake, TSMC announced a milestone in China, sketched out its long-term research, and gave an update on its use of machine learning for process automation.

The foundry is now producing 16-nm FinFET chips in its new Nanjing fab several months earlier than planned. The first phase in place includes a spaceship-like cafeteria, tubular office building, and 20,000-wafers/month fab that rivals Apple’s new headquarters in flashy design, though not scale. A second phase eventually will double production.

Meanwhile, TSMC researchers are progressing on designs of stacked nanowires as nanosheets for a next-generation transistor suitable for work at 2 nm and beyond. The design sports better electrostatics than FinFETs and can be optimized for power and performance by adjusting device width.

The foundry sees germanium as a strong candidate to replace silicon, providing lower power at the same speed. It achieved a record-low contact resistance using the material in a CMOS-compatible dielectric.

TSMC is exploring a variety of 2D back-end materials including molybdenum disulfide for their atomically smooth surfaces. They also are examining novel ways to enlarge copper grains to reduce resistance in interconnects. In addition, they are working on a selective dielectric-on-dielectric deposition process to enable self-aligning of copper vias.

In memories, they are exploring embedded MRAM for use beyond the 22-nm node, possibly with alternative magnetic structures. For embedded ReRAM beyond 40 nm, high-density crossbars are seen as an energy-efficient approach, especially for AI accelerators.

In terms of automation, TSMC is embracing machine learning to systematically analyze its wealth of wafer-processing data. It already tunes process recipes for specific tools and products. It also tracks and classifies process variations in an effort to automate the discovery of whether a problem is in a tool, process, or material.

The company has a library of more than 50,000 process recipes and tens of millions of control charts. Just how TSMC is applying machine learning to its automation tasks and with what products was unclear — no doubt, still something of a work in progress, perhaps with some secret sauce.