TSMC Updates its Silicon Menu

　　TSMC reported progress in 7 nm and extreme ultraviolet (EUV) lithography and bolstered a planar process that competes with fully depleted silicon-on-insulator at an annual event here. It also gave updates on its work in packaging and platforms for key market segments.

　　The foundry, celebrating its 30th anniversary, expects to tape out more than 10 7-nm chips this year and start volume production with the process next year. The chips include a quad ARM A72 core processor running at up to 4 GHz — possibly Huawei’s Kiron mobile processor — a CCIX development platform, and an unnamed ARM server processor.

　　TSMC sketched out what it called a relatively simple process of porting design rules and IP to an N7+ process using EUV that it could put into production in 2019. The process can deliver 20% greater density, 8–10% higher speeds, or 15–20% less power than its current N7 node. Compared to its 16FFC process, N7+ can enable 30% higher speed or 50% less power on an ARM A72 core, said Cliff Hou, vice president of R&D for design technology at TSMC.

　　The foundry will provide a utility to port immersion design rules to the EUV process that will “clean up most of the layout differences,” said Hou. Overall, the work of moving from N7 to N7+ should represent about a third of the effort of migrating to a new node, he added.

　　TSMC maintains four market-specific platforms with unique process features and IP. The leading-edge process is focused mainly on a high-performance computing platform that supports greater overclocking, lower resistance metal interconnects, tailored caches, and libraries. “We make the HPC flow really work for servers,” said Hou.

　　Targeting chips for the Internet of Things as well as 5G cellular, TSMC added a 22-nm ultra-low leakage (ULL) variant to its 22-nm ultra-low power (ULP) planar process announced in March. The two processes should be available next year, with Spice models ready by the end of 2017 and IP blocks ready in the first quarter of 2018.

　　The 22ULL process includes analog and RF improvements to serve millimeter-wave 5G chips as well as embedded memories optimized for low leakage. It supports parts running at 0.8 V and lower voltages for power management ICs. The node could provide a 5% optical shrink and lower power by 25% compared to designs made in a 28HP+ process.

　　In between its 7- and 22-nm nodes, TSMC is developing a 12FFC process that should be ready for production in 2019 using a new six-track (6T) standard cell library, down from 9T and 7.5T on the 16FFC node. The 12FFC process could shrink area 14% to 18% or provide 5% more speed.

　　The talks showed that TSMC is working multiple levers to eke out gains, said G. Dan Hutcheson of VLSI Research. “They are getting density, power, and speed improvements — things some people say no longer hold true with semiconductors.”

　　However, some of the results were less impressive than what TSMC estimated back in March, said Mike Demler, senior analyst at the Linley Group. The number of 7-nm tape outs and its performance gains, as well as power savings on 22ULP and performance gains with 12FFC, were all slightly lower than the foundry predicted six months ago, he said.

　　Samsung claims that N7 gives 45% improvement in area/power compared to N10, “ so I would expect better from TSMC’s N16 comparison,” said Demler. “Samsung foundry said [that] EUV will reduce 7-nm masks by 30%, but TSMC hasn’t provided any details.”

　　In a separate talk, Aart de Geus, chief executive of Synopsys, said that the foundry is offering a Baskin-Robbins of FinFET flavors that are “all distinct and have unique value.” For its part, Synopsys has participated in 70 FinFET designs, he added.

　　In packaging, TSMC said that it is working on a new variant of InFO, its wafer-level fab-out technique famously used in Apple’s latest A Series processors. InFO-MS will integrate logic and memory and is first being targeted for use with the latest high bandwidth memory (HBM2) in efforts among TSMC, Samsung, and SK Hynix.

　　Separately, Open-Silicon announced Tuesday that it has validated for use in system-in-package designs its HBM2 IP subsystem made using TSMC’s 16-nm process and its CoWoS 2.5-D chip stacking technology. It supports data rates up to 2 Gbits/second per pin. The company expects that a 7-nm version will hit 2.4 Gbits/s.

　　“Probably no company in the world has done as much to take us into 3D chip stacks as TSMC,” said Wally Rhines, chief executive for Mentor Graphics, which provides verification software for some of the foundry’s stacks.

　　Separately, TSMC reported progress using machine learning to achieve gains such as better route groupings in ARM A72 and A53 cores delivering up to 12% performance gains after synthesis. The foundry will release software scripts at the end of the year that its customers can use as a starting point on their own efforts to eke out more advances.

　　Cadence is applying machine learning in both verification and its Innovus place-and-route tools, said Anirudh Devgan, who manages two of the company’s divisions. “There are a lot of things that can be done using machine learning,” he said, noting 12% improvements in a 10-nm design.

　　In automotive, TSMC has a 16FFC platform ready that meets Grade 1 requirements and conforms to ISO-26262 and ASIL-B and -D standards. A 7-nm version will meet Grade 2 by next June. Processes from 40 nm to 22ULP will get an automotive services package by the end of 2018.