ASML Updates EUV Roadmap

　　SAN JOSE, Calif. — ASML showed stepwise progress in an update on the performance of its latest extreme ultraviolet (EUV) lithography system and its roadmap at the SPIE Advanced Lithography conference here. The talks showed that getting EUV into production will be a nail-biter, and keeping it useful in the next generation will require multiple field upgrades.

　　Over the weekend, the NXE 3400B system delivered 140 wafers/hour with a 245-W light source integrated in a system at the company’s headquarters in the Netherlands. ASML aims to tune the light source to 250 W for throughput of 150 wafers/hour and ship it to customers before June for use on 7-nm process nodes.

　　The lab demo was conducted without use of a protective pellicle on the wafers. The tests exposed a full field with 96 fields using a dose of 20 mJ/cm2.

　　A test using an 83% transmissive pellicle reached 100 WPH. ASML targets a 90% transmissive pellicle with 125-WPH throughput that can withstand a 300-W light source.

　　In its efforts to reduce defects from contaminating particles, ASML is working in parallel on the pellicle and a cleaner scanner that doesn’t need a pellicle. Last year, it eliminated all but six particles in a run of 10,000 wafers and aims to reduce it to one particle per 10,000 wafers next year.

　　The company targets a greater-than-90% uptime for the system by 2018–2019, when it should be in volume production. A day earlier, a Globalfoundries executive said that productivity levels were the key gating item on the first commercial use of the systems.

　　To meet the needs of 5-nm nodes, ASML plans three upgrades to the system delivered over the next two years.

　　Late this year, ASML aims to deliver a so-called overall and focus improvement package that enables overlays down to 1.7 nm, slightly below the required 1.9-nm target for 5 nm. In mid-2019, it plans a productivity enhancement package that boosts throughput to 145 WPH.

　　ASML is considering a model 3400C that it could deliver in 2020 with additional improvements, boosting throughput to 155 WPH. Details of the system are still under discussion with the small handful of big chip vendors who would be its users.

　　The NXE 3400B, large and ambitious as it is, is dwarfed by emerging plans for a follow-on tool nearly twice its size.

　　The 0.55-NA system aims to use larger optics, a higher-power light source, and faster internal pathways to kick out a maximum of 185 WPH while printing features with dimensions as small as 8 nm. If successful, the new system could print in one pass the kind of 3-nm features that today’s 3400B is expected to need three passes to create.

　　A talk on the new system here gave only a few glimpses at its progress but rammed home the point of its gigantic scope and scale. Optics maker Carl Zeiss SMT is now installing the first metrology system — the size of a small submarine — needed to make the system’s new and significantly larger lenses.

　　Zeiss is now constructing multiple buildings to house manufacturing for the optics. In November, it got a pledge of a $1.9 billion investment from ASML as part of their collaboration.

　　Meanwhile, engineers have finished their feasibility study and started design work on the system. It includes stands to help slide away a top module and remove a vacuum hull for servicing and upgrades, a process that, in an animation, looked akin to replacing an engine in a two-story locomotive.

　　Among other interesting details, the scanner requires a wafer cooling subsystem. That’s because it aims to focus two to three times more power on the wafer than the 3400B.

　　The subsystem is needed to ensure that heat generated by the light source deforms a wafer by no more than a nanometer while printing. Without it, a wafer could warp as much as 11.4 nm — larger than some of the features that it prints.

　　Jan Van Schoot, who leads the high-NA design for ASML, said that he sees no change in the existing power density needed for a protective pellicle.

　　Separately, ASML and Imec are exploring a stitching subsystem. It would knit two slightly deformed test images into one more perfect one to print. The process aims to speed throughput and help make increasingly large server chips.

　　The stitching concept has long been studied but never successfully implemented, noted one audience member in a Q&A session.

　　“Our study is ongoing and we may be showing more than we intend to do,” said Van Schoot. “We know it’s hard to do, so if we can’t implement it, we envision [that] less critical structures will be made at crossover points.”