Imec Aims 2-D FETs at Sub-5-nm Node

　　Designers can extend Moore's Law scaling beyond the 5-nanometer node by choosing two-dimensional anisotropic (faster with the grain) materials such as monolayers of black phosphorus, according to Imec (Leuven, Belgium). Researchers from the nonprofit semiconductor research institute described their findings at the annual Imec Technology Forum, held in San Francisco on the eve of Semicon West (July 11-13).

　　Imec’s demonstration project focused on field-effect transistors for high-performance logic applications as part of its Core CMOS program. Using co-optimization at the material, device, and circuit levels, Imec and its collaborators proved the concept using 2-D monolayers of anisotropic black phosphorus with a smaller effective mass in the transport direction. The black phosphorus was sandwiched between interfacial layers of low-k dielectric, with stacked dual gates deployed atop high-k dielectrics to control the atomically thin channels.

　　Imec demonstrated the co-optimization approach at the 10-nm node but says the architecture could function with sub-half volt (<0.5-V) power supplies and an effective oxide thickness of less than 50 angstroms (0.5 nm), allowing its FETs to extend Moore’s Law for high-performance logic applications below the 5-nanometer node.

　　The researchers predict the demonstrated architecture, materials, and co-optimization technique will yield reliable FETs with thicknesses all the way down to the single-atom level and gate lengths as short as 20 ?, advancing the nanowire FET as the successor to the FinFET. Imec is evaluating other materials besides black phosphor as prime candidates for extending nanowire FETs to atomic-level 2-D channels.

　　Beyond extending Moore’s Law scaling laws for FETs, the 2-D materials will enhance the development of photonics, optoelectronics, biosensing, energy storage, and photovoltaics, according to Imec.

　　The institute conducted the research in collaboration with scientists from Belgium’s Catholic University of Leuven (Belgium) and Italy’s Pisa University. Funding for the 10-nm demonstration came from the European Union’s Graphene Flagship research initiative along with Imec’s Core CMOS Program partners, which include GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, and TSMC.

　　For more details, see the free Nature scientific report “Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes,” in which Imec presents guidelines on choosing materials, designing the devices, and optimizing the performance of sub-10-nm high-performance logic chips. Imec explains that at gate lengths below 5 nm, the 2-D electrostatistics associated with gate stacking become more of a challenge than direct source-to-drain tunneling for 2-D-material-based FETs.