PCI Express Preps Shift to 32G

Release time:2017-06-08
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source:EE Times
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Copper interconnects will get another big turn of the crank with a Gen 5 PCI Express delivering 32 GTransfers/s as early as 2019. The PCI Special Interest Group announced the plan at an annual gathering, where it is still putting finishing touches on its 16 GT/s Gen 4 spec.

The news marks a significant acceleration for the widely used computer interconnect, which had hit the pause button for several years as the PC market slowed. It comes at a time when a variety of open interconnects such as CCIX, GenZ, and OpenCAPI may fragment efforts in the space.

PCIe Gen 5 will use 128-/130-bit encoding to deliver up to 128 GBytes/s over 16 4-GB/s lanes. It is expected to provide links for high-end GPUs, machine-learning accelerators, and Ethernet and Infiniband cards running at 400 Gbits/s.

PCI SIG members have already prepared a skeletal 0.3 version of the spec. It comes as the group is in final review of the 0.9 version of the Gen 4 standard.

The 32G spec comes at a time when the rise of giant data centers has been driving serdes interconnects to rates up to 56 Gbits/second.

“We can build off a lot of existing PHYs in the industry, leveraging other standards,” said Al Yanes, president of the PCI SIG. “A lot of the Gen 4 work is applicable and makes Gen 5 easier. Our electronics work group has come back very confident of the numbers and timeline.”

Engineers have yet to determine if the new spec will force new limits on the interconnect’s reach or require higher-cost board materials than FR4. But they have determined that it will be backward-compatible with the specs the group has developed over the past 25 years.

The PCI SIG is accelerating its road map after a lull from 2010–2017. Click to enlarge. (Image: PCI SIG)

PCIe Gen 5 represents a speed-up of work on fast I/O that the industry needs to meet system performance demands as it becomes more expensive to pursue Moore’s law, said Brad McCredie, an IBM fellow. The veteran microprocessor engineer is working on Power 9 that aims later this year to be the first commercial CPU to use PCIe Gen 4.

The industry “sat on PCIe Gen 3 for, I think, seven years … we had to nudge to get Gen 4 going,” said McCredie. “We need these high-performance buses to communicate with accelerators and provide cost improvements.”

“I think that it will be 2019 before the center point of industry gets to Gen 4, but if [the PCI SIG] stays on its slope, we’ll get to a version 10 of Gen 5 by 2020,” he added.

McCredie was reluctant to forecast the much-predicted end of copper interconnects. However, he did express hope that the Gen 4 connectors may still work at 32 GT/s and a copper PCIe spec beyond Gen 5 is possible.

“All the way back to Power 6 in 2005, we were saying that this [was] the last one,” he said. “But every time, I/O engineers sharpen their pencils and we get another doubling.”

Meanwhile, McCredie noted that IBM is a member of alternative open interconnect groups such as CCIX. “We’re evaluating all the open attach capabilities.”

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