New Xilinx CEO Touts 'Adaptive Computing'

　　Less than two months after taking the reigns at Xilinx, Victor Peng outlined a new strategy for the programmable logic stalwart that emphasizes technology for the data center and "adaptive computing," centered around what the company calls a new class of devices.

　　Claiming performance advantages over high-end CPUs and GPUs for applications related to Big Data and artificial intelligence, Xilinx will begin rolling out a new type of multicore chip next year that emphasize compute capability and with both software- and hardware-level programmability.

　　Xilinx — long the market leader in programmable logic devices — claims its adaptive compute acceleration platform (ACAP) goes far beyond the capabilities of FPGAs to deliver levels of performance and performance-per-watt unmatched by CPUs or GPUs. An ACAP consists of an FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC and one or more software-programmable compute engines, all connected through an on-chip network.

　　The first family of ACAP devices, codenamed project Everest, will be implemented at the 7nm node by TSMC. Initial tapeouts of Everest devices are expected to tapeout later this year, with initial customer shipments expected in 2019. Key customers have already received Xilinx development tools for Everest ACAP devices, the company said.

　　In an interview with EE Times, Victor Peng, Xilinx president and CEO, described the launch of ACAP devices as part of his broader strategy to move Xilinx "beyond FPGAs and supporting only hardware developers."

　　Peng said ACAP devices are aimed at a broad set of applications in Big Data and AI, including video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration.

　　The introduction of ACAP marks by far the most clear-cut attempt by Peng to put his stamp on the company he assumed the helm of in January, succeeding Moshe Gavrielov as CEO. Peng told EE Times he would emphasize data center as an end market more than his predecessor, both because it is seen as a significant growth area and also because it can benefit from what he said is "an orders of magnitude" performance-per-watt advantage that Xilinx can offer versus competitors.

　　In addition to a greater emphasis on data center, the strategy for Xilinx outlined by Peng includes shooting for accelerated growth in core markets such as automotive, wireless infrastructure, wired communications, broadcast, aerospace/defense, medical, test and measurement, consumer technologies, and others.

　　"While FPGA and Zynq SoC technologies are still core to our business, Xilinx is not just an FPGA company anymore," Peng said.

　　Peng also articulated a desire to market more directly to software developers, which he said can target ACAP-based systems using tools like C/C++, OpenCL and Python. Xilinx said an ACAP can also be programmable at the RTL level using FPGA tools.

　　An ACAP is also characterized by highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced serdes technology and RF-ADC/DACs, to integrated High-Bandwidth Memory, depending on the specific device, according to Xilinx.

　　ACAP products will ultimately encompass devices with more than 50 billion transistors, according to Peng. The launch is the result of four years of development by more than 1,500 with a total development price tag of more than $1 billion, he said.