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Cutting-Edge Passive Components Revolutionizing Next-Generation Power Supply Designs for AI Servers and Automotive Applications

　　To address the rapid trend toward higher power and higher density in power supply circuits, TAIYO YUDEN’s advanced capacitor lineup delivers "Compact & Low-Profile Designs," "Component Count Reduction," and "High Reliability."　　[AI Server Power Solutions]　　Supporting Next-Generation Power Architectures　　1. Compact, High-Capacitance MLCCs　　・Enable high-density power supply designs for low-voltage rails (0.6 V to 1.2 V) located close to processors.　　2. Embedded-Board Compatible MLCCs　　・Wide, flat electrode structures support stable component placement and multiple via connections.　　・Maximize PCB space savings and reduce parasitic inductance/resistance, supporting vertical power delivery architectures.　　3. Fully Integrated Manufacturing from Material Development　　In-house material technology ensures rigorous quality control and high reliability for mission-critical computing environments.　　[Automotive Power Solutions]　　High Reliability & Performance for ADAS and EV Applications (AEC-Q200 Qualified)　　1. High-Capacitance 3225 mm size (220 µF / 4 V) MLCCs　　・Industry-leading capacitance density in automotive-grade X7T (3225 size, 3.2 × 2.5 mm).　　・Accelerate the replacement of polymer capacitors through low ESR and low ESL characteristics—suppressing ripple, spikes, and heat generation while reducing mounting area.　　2. Soft-Termination MLCCs　　・Guarantees resistance up to 5 mm of flexure.　　・Low-Silver Filler Technology: Significantly suppresses ion migration in high-humidity environments while maintaining electrical performance and supply stability.

Key word：

TAIYO YUDEN

Release time：2026-09-10 15:21 reading：152 Continue reading>>

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Huawei Addresses Tau Scaling Heat Concerns as Kirin 2026 Tests Show ~55% Higher Density but Lower Power

　　Huawei is offering new data to support its chip-scaling approach, suggesting that higher transistor density does not necessarily come at the cost of higher power consumption. According to Global Times, a new paper by Huawei semiconductor segment chief He Tingbo on the company’s Tau (τ) Scaling Law presented measurements from the Kirin 2026 chip, with transistor density increasing by about 55% while power consumption fell across several key computing units at comparable performance.　　The paper, titled “Huawei’s τ Chip Was Supposed to Melt?” was recently posted by He on ChinaXiv, a preprint platform operated by the Chinese Academy of Sciences, STAR Market Daily notes. The paper addresses concerns that sharply increasing transistor density through folding could raise power density and make chips run hotter. Kirin 2026 measurements, however, showed power consumption falling 66% for the NPU, 58% for the GPU, and 41% for the CPU performance core at the same performance level, STAR Market Daily highlights. The NPU stood out, maintaining 29 TOPS while operating at a 63% lower frequency and reducing voltage from 0.85V to 0.55V, with power density falling 73%.　　LogicFolding Reduces Power by Cutting Data Movement　　According to the paper, much of a chip’s energy consumption comes from moving data rather than computation itself. As STAR Market Daily indicates, the Kirin chip reduces this burden by cutting data movement, which accounts for more than 80% of the energy consumed by a SoC module.　　LogicFolding tackles this by turning long horizontal interconnects into short vertical connections between stacked layers, significantly shortening signal paths and reducing interconnect capacitance and energy consumption, as noted by EE Times China. Measurements show that typical core routing lengths can be reduced by 20%, with some critical paths shortened by as much as 70%. The Kirin 2026 uses a 1.5-micrometer hybrid-bonding pitch and has around 50 million vertical interconnects, 10–15% of which are used for signal transmission.　　The paper also points to further scaling in future generations. Kirin 2027 test silicon has already reduced the hybrid-bonding pitch to 1 micrometer, with more than 100 million vertical interconnects. Over the next three years, Huawei plans to further shrink the pitch to 720nm while increasing the number of vertical interconnects to more than 200 million, EE Times China adds.　　LogicFolding May Face Key Engineering Challenges　　However, folding is not an ultimate solution and will require continued system-level engineering and iteration. He stressed that Tau is a time-scaling law, not an energy-scaling law: if designers use all the time saved to raise frequency, power consumption could instead increase. STAR Market Daily also notes that major engineering challenges remain, including hybrid-bonding pitch, wafer warpage, alignment accuracy, and EDA tool adaptation, with further work needed in these areas over the next three to five years.　　The Kirin 2026 is expected to power Huawei’s Mate 90 flagship series and its second-generation tri-fold smartphone, the Mate XT 2, both set to be unveiled in September, as noted by Commercial Times. The Mate 90 opened for pre-orders on August 31 and is expected to be officially unveiled starting September 7.

Key word：

Huawei

Release time：2026-09-08 15:38 reading：172 Continue reading>>

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ASML Japan to Boost Workforce 40% by 2030 to Support Rapidus, TSMC Advanced Chip Push

　　ASML’s EUV lithography systems are critical to advanced-node chipmaking, an area Japan is actively working to strengthen. According to Nikkei, ASML Japan President Shojiro Fujiwara said that the company plans to expand its domestic workforce from 500 to around 700 by 2030 to support growing advanced semiconductor production. Customers include Rapidus, which aims to begin Japan’s first mass production of 2nm chips in fiscal 2027. ASML has already doubled staffing at its Chitose office near Rapidus’ production facility from about 25 employees when it opened in 2024 to around 50, with further increases planned.　　Nikkei notes that ASML is considering expanding its presence in Kumamoto Prefecture, where TSMC already operates its first fab and is developing a second. According to Central News Agency, the second fab, originally planned for 6/7nm production, is now set to produce 3nm chips. TSMC is expanding its presence in Kumamoto further, with Reuters reporting that the company and Sony recently announced a US$4.69 billion joint venture for next-generation image sensors, targeting volume production in 2029.　　ASML is also seeing significant business growth in Japan. Its lithography system sales in the country climbed roughly 40% in 2025 to €1.2 billion ($1.4 billion). Beyond Rapidus and TSMC, Micron is also deploying ASML equipment at its Hiroshima Prefecture plant, Nikkei adds.　　Rapidus Pushes Ahead With 2nm Plans　　Rapidus, meanwhile, says its 2nm mass production remains on track. In a Reuters interview, CEO Atsuyoshi Koike said Rapidus is in talks with dozens of potential customers, while several major U.S. tech firms have shown interest and begun evaluations. The company said earlier this year that it had provided a pre-release PDK to early-adopter customers and established an environment for customer prototyping.　　Government backing is continuing ahead of the planned mass production. Japan’s Ministry of Economy, Trade and Industry (METI) is seeking an additional JPY 150 billion investment in Rapidus through its Fiscal Investment and Loan Program (FILP), bringing the government’s cumulative investment in the company to JPY 400 billion, according to Reuters.

Key word：

ASML

Release time：2026-09-07 14:38 reading：188 Continue reading>>

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TAIYO YUDEN Solutions for Automotive UWB Design Challenges

　　RF Devices for Automotive UWB　　Supporting the Evolution of Digital Keys　　The adoption of UWB digital keys, which combine high-precision positioning with robust security, is accelerating rapidly. However, automotive UWB development faces three key technical challenges: compact footprint for high-density mounting, RF interference mitigation, and high reliability in harsh automotive environments.　　TAIYO YUDEN provides RF devices featuring an ultra-compact form factor among the smallest in the industry and steep out-of-band noise attenuation. Enabled by our proprietary multilayer technology and rigorous automotive quality control, these solutions help resolve design challenges in next-generation mobility development.　　Ultra-Compact Form Factor Among the Smallest in the Industry: 1608 Size (1.6 × 0.8 mm)　　・Achieves an industry-leading compact footprint using proprietary multilayer ceramic technology, contributing to high-density mounting in automotive modules and enhancing antenna layout flexibility.　　RF Interference Suppression via Steep Attenuation Characteristics　　・Delivers both low insertion loss in the UWB band and steep out-of-band noise attenuation, ensuring stable operation in environments where multiple wireless systems coexist.　　High Automotive Reliability Qualified to AEC-Q200　　・Supports automotive system design and qualification through high manufacturing quality backed by fully integrated domestic production and PPAP compliance.　　Explore our full product lineup and detailed specifications on the Product Introduction Page.　　Technical details are available in our white paper.　　▶Download White Paper　　【Featured Automotive Solutions】　　Explore our automotive components supporting the evolution of autonomous driving and ADAS.　　Soft Termination MLCCs　　Addresses reliability concerns such as board flexure cracking to ensure stable operation in harsh automotive environments.　　Industry-leading High-Capacitance MLCCs for ADAS　　3225 size / 220 µF among the highest capacitance products in the industry, contributing to advanced electronic system integration.　　Conductive Polymer Hybrid Aluminum Electrolytic Capacitors (HTX-J/HVX-J Series)　　Combines solid polymer and liquid electrolyte technologies to achieve high-voltage capability, high capacitance, and low ESR stability.

Key word：

TAIYO YUDEN

Release time：2026-09-04 11:36 reading：318 Continue reading>>

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TSMC: SoIC, CoWoS to Drive 50× Compute by 2029; Silicon Photonics to Top 50% of Transceiver Market by 2027

　　TSMC is stepping up its technology roadmap to meet surging AI computing demand. According to TechNews, April Li, Global Head of AI and HPC Business Development at TSMC, said at SEMICON Taiwan 2026 that AI computing demand is growing fivefold annually, putting increasing pressure on compute capacity. In response, TSMC is integrating advanced process, 3DFabric, and silicon photonics into its HPC platform. Notably, the company expects SoIC and CoWoS integration to boost overall system computing performance to 50 times its 2024 level by 2029.　　As the report indicates, Li said heterogeneous integration is the only way to push beyond current computing limits. TSMC plans N2P-on-N3P 3D integration in 2026, followed by A14-on-A14 in 2029, with interconnect pitch shrinking to 4.5 microns.　　TSMC Advances COUPE and Silicon Photonics Design　　TSMC is also continuing to advance its COUPE technology. According to TechNews, its 2–4-micron bonding pitch limits transmission loss at 112 Gbps to just 0.06 dB, compared with 1.38 dB for micro-bumps, helping reduce power consumption and latency to 10–20 nanoseconds.　　As Mirror Daily indicates, TSMC’s self-developed COUPE platform uses TSMC-SoIC bonding technology to integrate electronic integrated circuits (EICs) with photonic integrated circuits (PICs), while supporting both grating couplers (GCs) and edge couplers (ECs). To further scale bandwidth, TSMC is pursuing two development paths. One will increase per-channel speeds from 200 Gbps to more than 400 Gbps while expanding channel counts from 16 to over 128, lifting total bandwidth from 3.2 Tbps to more than 12.8 Tbps. The other will expand wavelength-division multiplexing (WDM) from a single wavelength to 4, 8, 16, and beyond.　　The company is also addressing testing and design challenges as CPO moves toward broader deployment. According to Mirror Daily, TSMC has enabled wafer-level optical testing for edge-coupled devices, allowing defective dies to be screened out before costly CPO assembly. TechNews adds that TSMC has introduced an optical PDK that enables electronic-photonic co-simulation to address key silicon photonics design challenges, while Mirror Media notes that the PDK supports Cadence and Synopsys tools to help accelerate product development.　　Silicon Photonics Gains Ground as CPO Nears Mass Production　　Beyond TSMC’s technology roadmap, silicon photonics is moving toward broader adoption and large-scale CPO deployment. As noted by Central News Agency, TSMC Vice President of Advanced Packaging Technology and Service K.C. Hsu said optical transceiver architectures are undergoing a structural shift, with silicon photonics expected to account for more than 50% of the optical transceiver market by 2027. CPO represents the next step, with some suppliers expected to begin mass production in the second half of 2026.　　Hsu described optics as the “nervous system” of data centers as demand for high-speed connectivity grows. As noted by Central News Agency, he said optical transceiver sales rose 25% in 2025 and are expected to grow another 50% in 2026, while the high-end 100G-and-above market doubled in 2024 and expanded another 60% in 2025.　　Hsu noted that Taiwan’s silicon foundry ecosystem is already capable of producing optical engines at scale and with high precision, while real-world data and market validation are helping ease longstanding concerns over CPO reliability. The bigger challenge to large-scale deployment now lies elsewhere in the supply chain, including lasers, optical fibers, fiber connectors, and product testing, he said, as reported by Central News Agency.

Key word：

TSMC

Release time：2026-09-01 15:44 reading：250 Continue reading>>

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Intel’s Advanced Packaging, Led by EMIB-T, Set to Hit Its Stride in 2029; DRAM Manufacturing Ruled Out

　　Intel is gaining momentum in advanced packaging, with tech giants such as Google reportedly showing interest in its EMIB (Embedded Multi-die Interconnect Bridge) technology amid ongoing CoWoS supply constraints. Citing CFO David Zinsner’s remarks at Deutsche Bank’s 2026 Technology Conference on August 26, Investing.com reports that Intel expects advanced packaging revenue, led primarily by EMIB-T, to ramp in 2H27, become a steady contributor in 2028 and hit its stride in 2029.　　Memory was another key topic at the conference, as AI reshapes the strategic importance of memory. Tom’s Hardware previously reported that Intel CEO Lip-Bu Tan had hinted at a potential return to the memory market. Zinsner, however, clarified that Intel has no plans to re-enter DRAM manufacturing, according to Investing.com.　　Advanced Packaging Eyes 40% Gross Margin　　Notably, Zinsner highlighted the scale and profitability potential of Intel’s expanding advanced packaging business. According to Investing.com, the opportunity could be worth several billion dollars per customer annually, with the business targeting around 40% gross and 30% operating margins. Its relatively low capital intensity versus front-end manufacturing could also support strong ROIC, he added.　　In Zinsner’s words, Intel is “already eating our own dog food” with EMIB, indicating that the company is already deploying the technology in its own products. Building on EMIB, EMIB-T eliminates the need for an interposer, further enhancing the technology’s appeal and potential for broader adoption, he said.　　According to Wccftech, Intel’s Clearwater Forest, or Xeon 6+, CPU features twelve EMIB tiles using 2.5D packaging. The design integrates three active base tiles with two I/O tiles and twelve compute tiles. The I/O tiles are built on Intel 7, while the active base tiles use Intel 3 and the compute chiplets are manufactured on Intel 18A, the report explains.　　SK hynix Veteran’s Appointment Signals Intel’s Packaging Push　　Lip-Bu Tan’s appointment of former SK hynix CEO Seok-Hee Lee as Intel Foundry’s executive vice president could fuel speculation that Intel is considering a return to memory manufacturing. However, according to an Investing.com transcript, Intel CFO David Zinsner instead pointed to Lee’s appointment as a strong vote of confidence in the growth potential of EMIB-T.　　Bringing in an executive of Lee’s caliber to lead the business underscores Intel’s confidence in the opportunity and its long-term prospects, he added.　　Intel Stays Out of DRAM Manufacturing　　Notably, while Intel is developing memory-related technologies such as XHBM and Z-angle Memory (ZAM), Zinsner pushed back on speculation that the chipmaker plans to return to memory manufacturing.　　According to Investing.com, he said Intel has no plans to resume DRAM production. Instead, Intel is working with three major memory players on AI-focused products and architectures designed to ease memory bottlenecks. Management emphasized that the company’s focus will remain on system-level memory solutions rather than manufacturing memory itself, according to the Investing.com transcript.

Key word：

Intel

Release time：2026-08-31 16:02 reading：254 Continue reading>>

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Samsung’s 4nm GAIA Could Mark First PIM Commercialization in AI PCs, Mass Production as Early as 2027

Samsung is exploring a new approach to boost AI performance and efficiency on PCs. According to ZDNet, Samsung showcased its LPDDR5X-PIM paired with an edge AI accelerator SoC at Hot Chips. The company’s AI PC chipset under development, known as “GAIA,” is expected to incorporate LPDDR5X-PIM, which integrates computing capabilities directly into memory. This would mark the first integration of Processing-in-Memory (PIM) into an actual AI PC chipset. If GAIA reaches mass production, it could also become the first commercial application of PIM beyond the research and validation stage, the report notes.　　GAIA is an AI accelerator for AI PCs being developed by Samsung Electronics’ System LSI division. Built on Samsung Foundry’s 4nm process, the chip is optimized for AI workloads. ZDNet adds that Samsung has reportedly provided GAIA prototypes to major PC makers, including Lenovo and HP, for performance validation, with mass production potentially beginning as early as next year.　　LPDDR5X-PIM Delivers Up to 3.01x Higher Output in Testing　　The key to the approach is reducing data movement. As the report explains, LPDDR5X-PIM adds computing capabilities directly to low-power LPDDR5X memory, allowing some data to be processed where it is stored rather than repeatedly transferred between memory and CPUs or GPUs. This can ease AI computing bottlenecks while reducing power consumption.　　Samsung validated the SoC with both LPDDR5X and LPDDR5X-PIM, with PIM showing clear performance gains. LPDDR5X-PIM completed the test workload in 5.4 seconds versus 12.3 seconds for conventional LPDDR5X, a 2.28x improvement, while output jumped 3.01x from 27.0 to 81.3 per second, the report notes. ZDNet adds that Samsung previously said simulations showed up to 6.2x higher AI matrix-computation performance than conventional memory. These characteristics make LPDDR5X-PIM particularly suited to on-device AI, where laptops and smartphones face tight power and thermal limits.　　GAIA Could Put PIM Commercialization to the Test　　Samsung has been extending PIM technology across its memory portfolio, according to ZDNet. The company has introduced HBM-PIM for servers and integrated PIM with LPDDR for mobile applications. However, technical and ecosystem challenges have continued to limit its adoption in commercial products, the report adds. GAIA could therefore serve as a key test of PIM’s commercial potential. Sources cited by ZDNet note that if GAIA moves into mass production after customer validation in the AI PC market, PIM could evolve from a next-generation memory technology into a key solution for on-device AI.　　Samsung is also lowering barriers to PIM commercialization. As noted by Seoul Economic Daily, its Address Alignment Mode (AAM) allows LPDDR5X-PIM to work with existing DRAM memory controllers, reducing the need for major system changes. The report adds that the first JEDEC specification for next-generation LPDDR6-PIM is nearing finalization, as Samsung looks to expand PIM from a proprietary solution into a standardized memory technology.　　Meanwhile, SK hynix is also advancing PIM-based AI solutions. At CES 2026, the company showcased AiMX, an AI accelerator prototype built around its GDDR6-AiM PIM chip and designed for LLM workloads. The company also demonstrated other computational-memory technologies, including Compute-using-DRAM (CuD) and CMM-Ax.

Key word：

Samsung

Release time：2026-08-27 13:46 reading：423 Continue reading>>

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NOVOSENSE shares insights into automotive ultrasonic sensing at 2026 APEC 44th Automotive Dialogue

　　NOVOSENSE shared its latest insights into automotive AK2 ultrasonic radar sensor ICs at the 44th Automotive Dialogue of the Asia-Pacific Economic Cooperation, or APEC, held in Dalian, Liaoning province, China, from Aug 19 to 21.　　The meeting brought together representatives from government departments, industry associations and companies across APEC economies. Discussions focused on automotive market, policy and industry trends in the Asia-Pacific region, resilient and transparent automotive supply chains, the development of the hydrogen vehicle industry, and opportunities and challenges in advanced vehicle technologies.　　Liangfan Wang, technical marketing lead for the signal chain product line at NOVOSENSE, delivered a presentation on technology trends and practical solutions for AK2 ultrasonic radar sensor ICs, exchanging ideas with participants on the challenges and opportunities in automotive intelligent sensing.　　Shift toward digital architectures　　Automotive ultrasonic radar is moving from analog to digital architectures. Compared with the conventional AK1 analog architecture, AK2 uses digitally encoded modulation and echo signal processing to improve detection range, measurement accuracy and resistance to interference.　　Its interface has also evolved from point-to-point connections to a shared bus that supports coordinated operation among multiple sensors. AK2 ultrasonic radar has been applied in ultrasonic parking assist, automatic parking assist and automated valet parking systems.　　Development of multidimensional sensing　　Automotive ultrasonic sensing is expanding from 1D and 2D ranging toward 3D and 4D sensing. Its applications are also extending to low-speed automatic emergency braking, obstacle-type detection, road-surface classification and minor-impact detection.　　The technology continues to provide advantages in short-range sensing while working alongside millimeter-wave radar, ultra-wideband technology and cameras.　　Bumper-level sensing cycles are being reduced to less than 100 milliseconds, allowing vehicles to detect obstacles earlier and improving the efficiency of automated valet parking. This requires sensor ICs to provide stronger coordination among multiple transmit and receive channels, as well as greater resistance to interference.　　Further improvements are also required for object classification, road-surface recognition, sensor contamination detection and near-field blind-zone reduction. These functions require access to raw sensing data at different stages of signal processing.　　At the system level, MCU-less designs, two-wire DSI3 connectivity and direct-drive architectures can help reduce component and wiring-harness costs. The DSI3 architecture carries power and communication over the same pair of wires, while the direct-drive architecture removes the need for an external transformer.　　Flexible encoding reduces sensing time　　NOVOSENSE uses an arbitrary frequency pattern generator to provide fixed-frequency transmission, linear and nonlinear frequency encoding, and combined frequency-shift keying and chirp encoding.　　The solution supports multiple transmit and receive operation to improve resistance to interference. A bumper scan can be completed within two scanning cycles.　　Raw-data access extends the sensing range　　NOVOSENSE provides a configurable data-upload path with selectable decimation ratios ranging from 1× to 16×. Data can be compressed by the MCU before being uploaded through the DSI3 interface.　　Available data includes ADC raw data within a 2-millisecond window, post-mixing in-phase and quadrature data, and envelope data captured before and after an event.　　A time-varying low-noise amplifier automatically switches gain to reduce near-field saturation. The solution covers detection distances ranging from about 10 centimeters to 6.5 meters.　　DSI3 supports cross-brand interoperability　　NOVOSENSE has developed a cross-brand interoperability architecture based on the standard DSI3 protocol. It supports combinations of NOVOSENSE devices and other industry-standard DSI3 devices, as well as point-to-point, parallel and daisy-chain configurations.　　The NSUC1800 supports vendor-defined Command and Response Mode commands, while the NSUC1802 provides a DSI3 buffer of 2 kilobytes per channel. The two products address different requirements for functional expansion and flexible data access.　　About the APEC Automotive Dialogue　　Established in 1998, the APEC Automotive Dialogue provides a regular communication platform for government authorities and automotive industry representatives from APEC economies. It promotes exchanges and cooperation in areas including development strategies, standards and regulations, and technological innovation.

Key word：

NOVOSENSE

Release time：2026-08-26 14:03 reading：496 Continue reading>>

Trade news

NVIDIA Reportedly Eyes More Than 15% Price Hikes for Vera Rubin, Grace Blackwell Servers in Early 2027

　　NVIDIA is reportedly moving to raise prices across its AI server ecosystem. According to Bloomberg, sources say prices for servers powered by NVIDIA’s AI chips will increase by more than 15% for some of its biggest customers. The hikes will apply to systems shipped early next year, including those featuring NVIDIA’s flagship Vera Rubin and Grace Blackwell chips, with the size of the increase varying by chip generation and memory configuration.　　Server manufacturers that build systems under contract for major data center operators, including Microsoft, Alphabet’s Google, and Oracle, have reportedly informed customers of the upcoming increases. The move comes as memory supply remains a key consideration for AI systems. Wccftech notes that analysts believe NVIDIA may have secured multi-year agreements with SK hynix and Micron for HBM and DRAM supplies.　　The higher prices are also raising concerns about rising costs for AI data center development and operations worldwide. Chosun Ilbo, citing The Information, notes that the increases could add at least US$5 billion (approximately KRW 7 trillion) to the cost of building a 1-gigawatt (GW) AI data center.　　Memory Supply Emerges as Key AI Chip Pricing Factor　　Meanwhile, Hankyung notes that higher NVIDIA AI chip prices could weigh on the broader AI data center ecosystem, potentially slowing demand and bringing the rise in memory prices to a halt.　　Analysts cited by Hankyung say NVIDIA’s decision to pass higher costs on to customers highlights the growing influence of memory suppliers. With memory supply increasingly affecting both AI chip production volumes and pricing, its role in overall system costs is also expanding. Morgan Stanley notes that GPUs once accounted for more than 80% of AI server costs, but their share has fallen to roughly half that level in next-generation systems as memory-related costs rise rapidly.　　According to TrendForce, server DRAM contract prices are expected to rise 13–18% quarter-over-quarter in 3Q26. With the market remaining undersupplied, memory suppliers may continue revising quotations upward throughout the rest of the quarter. Overall, TrendForce expects server DRAM contract prices to continue rising each quarter from the second half of 2026 through the second half of 2027, although the pace of increases is likely to moderate.

Key word：

NVIDIA

Release time：2026-08-25 15:11 reading：416 Continue reading>>

Trade news

SK hynix Reportedly Builds Silicon Valley HBM Team to Boost Customer Co-Design With U.S. Big Tech

　　SK hynix is reportedly strengthening its HBM co-design capabilities in Silicon Valley as it deepens collaboration with global Big Tech customers. According to NewsPim, sources say SK hynix America operates an HBM Architect Design Team in San Jose, California, working directly with major U.S. customers on base-die design for HBM and 3D-stacked DRAM. The team develops next-generation HBM architectures around customer requirements, going beyond local technical support to collaborate throughout product development.　　Notably, NewsPim adds that SK hynix is expanding the team, offering annual salaries of US$150,000–US$260,000. The company is seeking experience in DRAM and HBM architecture, full-custom and digital co-design, power delivery network (PDN) analysis, and logic foundry design, with experience in 1x-nanometer DRAM and foundry nodes of 3nm or below preferred. Developing advanced, customer-tailored HBM architectures for future products is among the team’s core responsibilities, the report notes.　　The San Jose location also supports this strategy. As NewsPim notes, NVIDIA and AMD are headquartered in nearby Santa Clara, while Broadcom has operations in San Jose. Positioning HBM engineers near these major AI chip design hubs allows SK hynix to work directly with customers on next-generation products and quickly relay their requirements to development teams in South Korea.　　SK hynix is already deepening such collaboration with NVIDIA. Chosun Ilbo notes that the two companies are jointly developing next-generation memory for AI factories, expanding their partnership beyond supplying existing HBM toward developing advanced memory aligned with NVIDIA’s next-generation roadmap.　　Customer Co-Design Reshapes HBM Competition　　Customer co-design is expected to become even more important with HBM4 and future generations. As NewsPim notes, increasingly diverse AI accelerator architectures are driving different requirements for HBM capacity, bandwidth, and power, making early co-optimization of AI chips and memory increasingly important.　　This is also reshaping HBM competition. Memory suppliers that participate early in customers’ next-generation AI chip development can incorporate specific requirements into their designs, while co-developed HBM may raise barriers for rivals seeking to enter the same supply chain later. As the report points out, such collaboration is becoming increasingly important for securing next-generation HBM orders.　　The trend extends beyond SK hynix. Seoul Economic Daily notes that Samsung is recruiting base-die designers as customer-specific optimization for AI accelerator vendors becomes increasingly important with HBM4. The company is also hiring application engineers to evaluate HBM on AI accelerator systems and support key customer qualifications, with the aim of shortening the certification process.

Key word：

SK hynix

Release time：2026-08-20 11:44 reading：460 Continue reading>>

model	brand	Quote
RB751G-40T2R	ROHM Semiconductor
MC33074DR2G	onsemi
CDZVT2R20B	ROHM Semiconductor
BD71847AMWV-E2	ROHM Semiconductor
TL431ACLPR	Texas Instruments

model	brand	To snap up
ESR03EZPJ151	ROHM Semiconductor
BU33JA2MNVX-CTL	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
IPZ40N04S5L4R8ATMA1	Infineon Technologies
TPS63050YFFR	Texas Instruments
BP3621	ROHM Semiconductor

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