EU Agency Offers Corrective for IoT Security ‘Market Failure’

发布时间:2017-06-12 00:00
作者:Ameya360
来源:EE Times
阅读量:862

  Products connected to the Internet of Things should meet a minimum defined level of security and should be labeled accordingly to promote consumer trust, according to the European Union Agency for Network and Information Security (ENISA). The agency worked with Infineon, NXP, and STMicroelectronics to produce a position paper that reflects the European semiconductor industry’s IoT security concerns and provides guidelines for policymakers.

  The paper warns of a current “market failure” for cybersecurity and privacy: Incorporating security measures increases cost, but buyers are reluctant to pay more for solutions with added security. There is thus “no basic level, no zero level defined for the security and privacy of connected and smart devices,” the authors state.

  “The past and current attitude of the private sector is mitigated, but weighs more strongly against including security in IoT devices,” said Michela Menting, digital security research director at ABI Research. “This is because security is seen as costly, and lengthens time-to-market. The argument there is often one of stifling innovation, especially if standards become regulatory requirements, and impeding market growth.”

  Menting says this attitude may be softening.

  “With cybercrime rising quickly in the IoT domain (i.e. WannaCry and Mirai) having affected some control systems, there is mounting realization that no-security will be just as costly, and could be reputationally damaging as well,” she said. “The attitude is slowly swaying the way of security, but at a terribly slow pace.”

  The EU already has several projects in the IoT security space, including the Alliance for the Internet of Things Innovation (AIOTI) who are putting together baseline requirements for security and privacy, and a proposed IoT security trust label similar to current energy efficiency ratings for appliances (ratings from A to D), which is under discussion.

  “The forthcoming GDPR [General Data Protection Regulation] and NIS [Network Information Security] directives will also have a significant impact,” Menting said. “Data coming out from connected IoT devices, which might be deemed personal, will need to be protected according to the GDPR, and critical infrastructure operators that are deploying connected industrial control systems will also need to make sure that they have adequate security measures in place, not just critical safety ones.”

  The new ENISA position paper urges the European Commission to ensure minimal security requirements for connected devices. It recommends establishing baseline requirements for security and privacy that would set reference levels for trusted IoT solutions depending on the complexity of the device. A third party should evaluate and certify devices, and those that meet the required security level should be identified with an EU Trust Label, the paper suggests.

  “Ideally, the use of the label should be mandatory as a symbol of trust for citizens, consumers and businesses in the connected world,” the paper states. “An obligatory reference framework and an associated label would ensure appropriate levels of security for products and services. This would further lead to a level playing field for the entire industry.”

  Another priority should be the development of reliable security processes and services, such as providing small and medium enterprises (SMEs) with information and training on security solutions, according to the paper.

  The authors also outline the need for future revisions of the security requirements that would step them up in stages beyond the baseline level. To address the economic challenges of adding security to products, they suggest incentives such as the inclusion of a “Digital Security Bonus” in insurance policies, as well as penalties “for dealing with vendors of security products and services that abuse established practices.”

(备注:文章来源于网络,信息仅供参考,不代表本网站观点,如有侵权请联系删除!)

在线留言询价

相关阅读
Intel Ceding Leadership in EUV
The few chipmakers that lead technology development are betting that by next year extreme ultraviolet lithography (EUV) will take transistor densities on semiconductors another step closer to their physical limits.Intel, once the world’s biggest chipmaker, appears to have given up efforts to lead the pack in EUV. The company was among the first to start EUV development in the late 1990s.Intel will not be inserting EUV anytime soon, according to Mark Li, an electronics engineer and analyst with Bernstein. The company is having difficulties ramping 10nm, and EUV in Intel’s 7nm, expected several years from now, remains an open question, he adds.In the meantime, Samsung and TSMC are pressing ahead with EUV, albeit cautiously. While Samsung and TSMC are developing EUV for introduction in 2019, the rest of the world’s major chipmakers appear to be falling behind.Intel, for now, appears to be a distant third in the race.“Intel has effectively lost its manufacturing leadership,” according to Mehdi Hosseini, an analyst with Susquehanna.Globalfoundries last year said it expects to use EUV tools in 2019 production flows to make contacts and cut masks.Samsung will introduce 7nm, the newest node, later than TSMC but with EUV, according to Li. While TSMC's enhanced version of 7nm, called 7nm+, will be slightly later with fewer EUV layers, the flexibility of having both EUV and non-EUV versions will be an advantage, he says.Samsung has consistently planned for EUV insertion with a minimum of 8-10 layers at 7nm compared with a few layers that TSMC has planned at 7nm+, according to Hosseini.Intel may be biding its time until the technology is more mature.The company told EE Times last year that it is committed to bringing EUV into production as soon as the technology is ready at an effective cost. Intel may not insert EUV into its process technology until late 2021, according to a forecast from Bernstein.“It now appears that Samsung's aggressive plans have backfired, and prospective customers are not so pleased with Samsung's 7nm process recipe” Hosseini said.Hosseini added that Susquehanna doesn't believe that Globalfoundries had gained much traction at 7nm. Globalfoundries subsequently announced that it suspended work on 7nm node, and will lay off nearly 5% of its workforce and make its ASIC group a wholly-owned subsidiary so it can partner with one of the remaining 7nm foundries.The chip industry’s cautious adoption of EUV lithography will probably not have an impact on TSMC’s business with Apple, according to Bernstein’s Li.“Though Apple may not be using EUV next year, we believe TSMC will retain Apple's exclusive processor business,” he said. “We also don't think this will negatively impact TSMC's EUV plan.”TSMC will be able to bring EUV to mass production in the second half of 2019 as many customers, including mobile, GPU and cryptocurrency miners, are interested in 7nm+, Li said.For now, TSMC leads its competitors with the rollout of 7nm technology, and that’s one of the key reasons the company has been able to increase business with Apple and other key customers, according to Susquehanna's Hosseini.“TSMC appears to be winning most of the leading-edge design wins due to better 7nm process technology performance, lower power consumption and better area density,” he told EE Times. “TSMC’s 7nm is expected to account for more than 20 percent of the company’s revenue in the December quarter as the customer mix includes more than 50 different product tapeouts for diverse applications including APs, GPUs, server CPUs, network processors and FPGAs.”Technology leadership should help TSMC diversify its customer base in the future.“TSMC will increasingly benefit from non-smartphone markets over time as new growth drivers start to inflect: 5G basestations, cloud computing, autonomous vehicles and AI are all nascent but important long-term opportunities in high-performance compute that require leading-edge technology,” according to Arete analyst Brett Simpson.
2018-09-03 00:00 阅读量:908
 50 EUV Systems Set to be Shipped by ASML by 2019
Dutch semiconductor equipment vendor  ASML said Wednesday it is on track to ship 20 extreme ultraviolet (EUV) systems in 2018 and expects to ship at least 30 more in 2019.The company's estimates came as part of ASML's second quarter financial report, which included better-than-expected sales of EUV tools and overall sales of about $3.2 billion. "Gross margin was slightly above our guidance, reflecting the strength of our DUV and applications business and progress in EUV profitability," said ASML CEO Peter Wennink.ASML shipped four EUV systems in the second quarter, one more than forecast, as logic customers prepare to ramp next-generation devices starting later this year, Wennink said.EUV — the successor to the workhorse deep ultraviolet (DUV) technology in advanced semiconductor manufacturing — is finally on the cusp of production after years of delays. Leading-edge semiconductor manufacturers include Samsung, Intel and TSMC are planning to use EUV in volume production beginning in the next year, though concerns remain about the availability of the EUV power source and other items in the EUV supply chain, including pellicles.ASML says it has now demonstrated four-week availability of well above 85% on a number of its new NXE:3400B EUV systems and is executing several programs to improve consistent availability to over 90% in 2019.Wennink said ASML's deep-ultraviolet lithography business continues to thrive, driven largely by the memory market, which  continues to require a significant number of lithography systems at least throughout this year and into 2019. After an excellent first half of 2018, we expect the second half."After an excellent first half of 2018, we expect the second half to be stronger, with improved profitability and continued growth from Q3 to Q4,” Wennink said.For the third quarter,  ASML said it expects sales of between 2.7 billion and 2.8 billion euro (roughly $3.15 billion to $3.26 billion).
2018-07-23 00:00 阅读量:913
ASML Updates EUV Roadmap
  SAN JOSE, Calif. — ASML showed stepwise progress in an update on the performance of its latest extreme ultraviolet (EUV) lithography system and its roadmap at the SPIE Advanced Lithography conference here. The talks showed that getting EUV into production will be a nail-biter, and keeping it useful in the next generation will require multiple field upgrades.  Over the weekend, the NXE 3400B system delivered 140 wafers/hour with a 245-W light source integrated in a system at the company’s headquarters in the Netherlands. ASML aims to tune the light source to 250 W for throughput of 150 wafers/hour and ship it to customers before June for use on 7-nm process nodes.  The lab demo was conducted without use of a protective pellicle on the wafers. The tests exposed a full field with 96 fields using a dose of 20 mJ/cm2.  A test using an 83% transmissive pellicle reached 100 WPH. ASML targets a 90% transmissive pellicle with 125-WPH throughput that can withstand a 300-W light source.  In its efforts to reduce defects from contaminating particles, ASML is working in parallel on the pellicle and a cleaner scanner that doesn’t need a pellicle. Last year, it eliminated all but six particles in a run of 10,000 wafers and aims to reduce it to one particle per 10,000 wafers next year.  The company targets a greater-than-90% uptime for the system by 2018–2019, when it should be in volume production. A day earlier, a Globalfoundries executive said that productivity levels were the key gating item on the first commercial use of the systems.  To meet the needs of 5-nm nodes, ASML plans three upgrades to the system delivered over the next two years.  Late this year, ASML aims to deliver a so-called overall and focus improvement package that enables overlays down to 1.7 nm, slightly below the required 1.9-nm target for 5 nm. In mid-2019, it plans a productivity enhancement package that boosts throughput to 145 WPH.  ASML is considering a model 3400C that it could deliver in 2020 with additional improvements, boosting throughput to 155 WPH. Details of the system are still under discussion with the small handful of big chip vendors who would be its users.  The NXE 3400B, large and ambitious as it is, is dwarfed by emerging plans for a follow-on tool nearly twice its size.  The 0.55-NA system aims to use larger optics, a higher-power light source, and faster internal pathways to kick out a maximum of 185 WPH while printing features with dimensions as small as 8 nm. If successful, the new system could print in one pass the kind of 3-nm features that today’s 3400B is expected to need three passes to create.  A talk on the new system here gave only a few glimpses at its progress but rammed home the point of its gigantic scope and scale. Optics maker Carl Zeiss SMT is now installing the first metrology system — the size of a small submarine — needed to make the system’s new and significantly larger lenses.  Zeiss is now constructing multiple buildings to house manufacturing for the optics. In November, it got a pledge of a $1.9 billion investment from ASML as part of their collaboration.  Meanwhile, engineers have finished their feasibility study and started design work on the system. It includes stands to help slide away a top module and remove a vacuum hull for servicing and upgrades, a process that, in an animation, looked akin to replacing an engine in a two-story locomotive.  Among other interesting details, the scanner requires a wafer cooling subsystem. That’s because it aims to focus two to three times more power on the wafer than the 3400B.  The subsystem is needed to ensure that heat generated by the light source deforms a wafer by no more than a nanometer while printing. Without it, a wafer could warp as much as 11.4 nm — larger than some of the features that it prints.  Jan Van Schoot, who leads the high-NA design for ASML, said that he sees no change in the existing power density needed for a protective pellicle.  Separately, ASML and Imec are exploring a stitching subsystem. It would knit two slightly deformed test images into one more perfect one to print. The process aims to speed throughput and help make increasingly large server chips.  The stitching concept has long been studied but never successfully implemented, noted one audience member in a Q&A session.  “Our study is ongoing and we may be showing more than we intend to do,” said Van Schoot. “We know it’s hard to do, so if we can’t implement it, we envision [that] less critical structures will be made at crossover points.”
2018-03-01 00:00 阅读量:1316
EUV Defects Cited in 5-nm Node
  SAN JOSE, Calif. — Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5-nm nodes. They are applying an array of techniques to eliminate them but, so far, see no clear solution.  The news comes as Globalfoundries, Samsung, and TSMC are racing to rev EUV systems up to high availability with 250-W light sources for 7-nm production next year. The defects show that there’s no panacea for the increasing costs and complexity of making semiconductors.  The latest EUV scanners can print the 20-nm-and-larger critical dimensions that foundries plan at 7 nm, said Greg McIntyre, a patterning expert from the Imec research institute in Belgium. However, their ability to make finer lines and holes is unclear, he said in a talk at the SPIE Advanced Lithography conference here.  Optimists such as McIntyre believe that a basket of solutions will emerge for the so-called stochastic effects. Some skeptics see the results as one more reason to doubt that the expensive and long-delayed EUV systems will become mainstream tools for chipmakers.  A retired Intel lithographer predicted that engineers will be able to create 5-nm and even 3-nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.  The latest defects are cropping up at critical dimensions around 15 nm needed to make 5-nm chips for foundry processes targeting 2020. EUV maker ASML is preparing a next-generation EUV system for printing finer features, but those systems won’t be available until about 2024, it said at the event last year.  The random defects take many forms. Some are imperfectly made holes; others are tears in lines or shorts where two lines or two holes meet. Given their tiny dimensions, researchers sometimes spend days just to find them.  McIntyre outlined the challenges finding and eliminating the errors. For example, some researchers are proposing this week a standard way to measure the roughness of lines, one key to understanding the defects.  Another issue is that it’s unclear exactly what happens to resist materials when hit with EUV light. “It’s still unknown how many electrons are generated and what kinds of chemistries are created … we’re a little ways from a full understanding of the physics, so we’re doing more experiments,” said McIntyre, noting that researchers have tested as many as 350 combinations of resists and process steps.  “Manufacturing guys will get beat up incredibly over yield loss … if I was going to be responsible for this, I’d say it’s time to retire,” quipped one veteran lithographer during a Q&A session about the 5-nm defects.  A Globalfoundries technologist provided a more upbeat but sober assessment in another keynote. “It’s been a lot of hard work, and there’s a lot more hard work to come,” said George Gomba, a vice president of research at GF, recalling a nearly 30-year history of work on EUV.  Today’s NXE 3400 systems are “not meeting some roadmap conditions we desire, so there is still some uncertainty [at 7 nm]. If we do not make productivity and availability improvements, we may only be able to use EUV for the most aggressive processors.”  Gomba noted that the random defects at 5 nm include subtle 3D breaks and tears such as notches in lines. He also called for more work on so-called actinic systems that inspect EUV masks before lithographers cover them with protective pellicles.  “To get full use of EUV, we will need actinic inspection systems [still in development], maybe complementing e-beam mask inspection systems” that are available today.  In an interview, Borodovsky said that another factor that may be contributing to the 5-nm defects is a lack of homogeneity in the current EUV resist materials. Separately, he said that he supports work on direct e-beam writers because the complex phase-shift masks that EUV uses ultimately will balloon to eight times the price of today’s immersion masks.  Multibeam, a company formed by Lam Research founder David Lam, recently snagged $35 million in government funding for his e-beam technology. He hopes to have commercial systems in 2.5 years for niche applications, but versions suitable for high-volume manufacturing will take much longer, said Lam.  By 2024, defects could become so widespread that conventional processors will not be able to be made in leading-edge processes, said Borodovsky. Experimental chips using memory arrays with embedded computing elements could be more fault-tolerant, citingIBM’s True North chip and work by HP Labs with memristors.
2018-02-28 00:00 阅读量:942
  • 一周热料
  • 紧缺物料秒杀
型号 品牌 询价
MC33074DR2G onsemi
BD71847AMWV-E2 ROHM Semiconductor
CDZVT2R20B ROHM Semiconductor
RB751G-40T2R ROHM Semiconductor
TL431ACLPR Texas Instruments
型号 品牌 抢购
IPZ40N04S5L4R8ATMA1 Infineon Technologies
ESR03EZPJ151 ROHM Semiconductor
TPS63050YFFR Texas Instruments
BU33JA2MNVX-CTL ROHM Semiconductor
BP3621 ROHM Semiconductor
STM32F429IGT6 STMicroelectronics
热门标签
ROHM
Aavid
Averlogic
开发板
SUSUMU
NXP
PCB
传感器
半导体
相关百科
关于我们
AMEYA360微信服务号 AMEYA360微信服务号
AMEYA360商城(www.ameya360.com)上线于2011年,现 有超过3500家优质供应商,收录600万种产品型号数据,100 多万种元器件库存可供选购,产品覆盖MCU+存储器+电源芯 片+IGBT+MOS管+运放+射频蓝牙+传感器+电阻电容电感+ 连接器等多个领域,平台主营业务涵盖电子元器件现货销售、 BOM配单及提供产品配套资料等,为广大客户提供一站式购 销服务。