RISC-V Cores Get Support, Fees

发布时间:2017-05-05 00:00
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来源:EETimes
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Instruction sets may want to be free, but cores--maybe not so much. Startup SiFive announced a new embedded RISC-V core and a relatively simple way to access its processor cores on its Web site, however, they come with one-time licensing costs in the mid-six figures.

SiFive made its existing 32-bit E31 core and a new 64-bit E51 version available for one-time fees of about $300,000 and $600,000, respectively. An open source core called Rocket created by some of SiFive's founders remains available for free online. It can be used to configure and generate 32- and 64-bit processor cores.

The SiFive news comes just before the sixth workshop of the RISC-V open instruction set group, its first in China.

SiFive will have to compete with a wide range of cores from Cadence, Cortus, Imagination, Synopsys and Andes--which rolls out its first 64-but core next week. The existing players have more mature ecosystems and cores that also sell for less than a million dollars, said Linley Gwennap, principal of the Linley Group (Mountain View, Calif.).

“I thought their original business model was the core would be open source, so they seem to have changed their business model…They are trying to innovate but at the end of the day everyone has costs,” Gwennap said.

“A year ago there was quite a debate if people would license a core if there was a free version, [but now] we’ve seen significant demand for customers who don’t want an open-source version but one better documented with a company behind it,” said Jack Kang, vice president of product and business development at SiFive.

SiFive provides just the processor core, but researchers at Berkeley and elsewhere have released other elements such as the TileLink interface. (Image: SiFive)
SiFive provides just the processor core, but researchers at Berkeley and elsewhere have released other elements such as the TileLink interface. (Image: SiFive)

The E31 and E51 come with a warranty the cores will hit a specified performance target as well as indemnification, documentation, test benches, constraint files and integration files. “The analogy here is with Red Hat that provides a package with support,” said Kang.

SiFive points to the value of making its silicon IP easy to access and royalty-free. Royalties are not a big issue for engineers who typically forecast their lifetime needs for a core and figure that into a total negotiated price," said Gwennap.

Datasheets and other detailed information to evaluate the cores, including FPGA bitstream models and an evaluation version of functional, synthesizable RTL for the E31 are freely available on the company’s Web site. The site also lets engineers configure cores and buy them after agreeing to a seven-page licensing contract online.

“The ability to try, configure and buy a core over the Web is unheard of, and there’s no royalties so you don’t have to figure out how many you are going to sell,” said Kang.

“You can buy all sorts of software online and can even set up an Amazon data center service with a few clicks, so why is the silicon IP industry so far behind?” asked Kang. “We have to get IP from others and it’s incredible how hard it is, so we have a chance to do something new for the industry,” he said.

Both the E31 and E51 can run at data rates up to 1.4 GHz in a 28 nm process. The E31 is roughly comparable to an ARM Cortex M3 or M4. The E51 creates a new entry-level for an embedded 64-bit core below ARM’s Cortex A53.

Neither core runs Linux, SiFive plans to roll out a separate U54 core for standalone processors running Linux later this year. It may roll out an additional E-series cores before the end of the year.

FreeRTOS, Project Zephyr and Apache Minute OSes have been ported to the current E31 core. The RISC-V architecture now has available a GCC compiler for C, a GNU debugger and other peripheral tools. SiFive provides an SDK and an Eclipse-based development environment.

“There’s been huge progress in the RISC-V ecosystem,” said Kang.

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正在乌镇举行的第六届世界互联网大会上,中国工程院院士、中国开放指令生态(RISC-V)联盟(CRVA)理事长倪光南发表演讲称,要推动开源的RISC-V成主流。倪光南表示,从世界的角度来看,两类架构的CPU已经占据市场。第一代是X86,英特尔和AMD两家公司掌握,在服务器等领域占有垄断地位;第二个是ARM,在移动领域有垄断的地位。不过他强调,X86架构是垄断的,ARM架构的授权费用又很高 ,“海思和国防科技大学买到的ARM终身架构授权需要花费很高,钱花的比较多。”作为中国开放指令生态(RISC-V)联盟(CRVA)理事长,倪光南表示要加强联盟的工作,避免碎片化,形成良性循环。“我们要迅速的培养基于RISC-V的新型开放生态,不要做历史包袱很重的ARM和X86。”对于RISC-V生态,目前阿里已经有所行动,今年7月份平头哥正式发布玄铁910,这也是目前业界最强的RISC-V处理器(单核性能达到7.1 Coremark/MHz,主频达到2.5GHz)。据介绍,玄铁910可以用于设计制造高性能端上芯片,应用于5G、人工智能以及自动驾驶等领域。另外,华为之前也表示,对RISC-V开发很有兴趣,而他们还是这个基金会的成员。以RISC-V现在的发展速度,2年后就要跟高通、苹果、三星、联发科等ARM公司抢智能手机处理器市场了,还有可能威胁低功耗笔记本处理器。5年后RISC-V指令的处理器就有可以进军服务器市场,到时候AMD、Intel这样的X86处理器公司也要担心了。
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