NAND Clash Spans Chip to Code

　　NAND flash has become a wonderful mess. Vendors are tripping over each other to deliver new chips in new form factors with new software faster than users can figure out what to do with them.

　　That was the view from the Flash Memory Summit, where a small but significant early-morning fire set off sprinklers and drenched hopes of an exhibit floor. A reporter snapped a shot of a melted computer rack attributed to a faulty extension cord at an Innodisk booth. No one was hurt.

　　No one needed a demo to see that the main stars of this show were a handful of 3D-NAND chips. Samsung promised a Tbit chip next year; Toshiba showed a 96-layer, 768-Gbit chip also shipping next year; and Micron described its 512-Gbit chip. All three said that they will deliver versions packing four bits per cell, along with Western Digital, which shares the Toshiba design.

　　Details on all the chips were scarce with techniques for creating big NAND stacks considered secret sauce. Creating even holes through the many layers and getting cells from top to bottom delivering the same performance are the top challenges, said Jeff Oshima, a flash veteran from Toshiba, in a brief backstage interview with EE Times.

　　Toshiba uses different cell designs on different segments of the stack, and its 96-layer design is based on stacks of stacks, said Oshima. He declined to say how many different cell designs or stacks Toshiba uses.

　　The move to four bits/cell will have an impact on the number of write cycles for the chips. But Oshima said that users have indicated that they are willing to relax their endurance requirements to get greater capacity.

　　Micron said that its 512-Gbit chip has a 16–20% higher density in Gbits/mm2 than two of its larger competitors. However, it did not provide details of its chip’s size or status or when it will support four bits/cell.

　　In a sign of all the activity, Lam Research raised its estimates of capital spending on NAND over the next five years to $70 billion, up from $50 billion. The estimate is based on projected 40% bit growth for NAND over the period.

　　“3D NAND has a lot of legs … We see a path to more than 100 layers,” said Rick Gottscho, CTO of Lam Research, which makes the deposition and etch systems to make the chips.

　　“You want as many layers in a single process as possible before you stack on another set. We believe the most cost-effective and highest yield comes from a single stack … so there will be a trend to push to as many layers as you can.”

　　The thickness of individual layers is the gating item for the chip design, said Jim Handy, market watcher with Objective Analysis (Los Gatos, California). Samsung’s disclosure of the stair-step design using nine rather than four holes for its current 512-Gbit chip was the most interesting revelation from the Korean giant, he added.