TSMC Tips 7+, 12, 22nm Nodes

发布时间:2017-03-14 00:00

Trying to cover the waterfront, TSMC disclosed plans for new high-, mid- and low-end processes at an annual event here. They included an enhanced 7nm FinFET node using extreme ultraviolet lithography, a 12nm upgrade of its 16nm process and a 22nm planar technology — its answer to fully depleted silicon-on-insulator (FD-SOI).

The foundry also described enhancements to its two chip-stacking techniques, advances in RF CMOS and work in transistors and materials, paving the way to a 3nm node and beyond. In addition, it previewed design capabilities using machine learning that it will offer before the end of the year.

Among its achievements, TSMC noted 76 percent yields on the 256Mbit SRAM made in its first-generation 7nm node, which will be in volume production next year. It also reported that an ARM Cortex-A72 processor in the node exceeded 4GHz using a new design flow.

The proliferation of different nodes, sub-nodes and platforms threatens to create a dizzying array of options. TSMC has clearly focused on easing migrations for designers, sometimes at the expense of advances measured in single digits.

The Taiwan company, already the world’s largest foundry by far, expects to ship 11 million 12-inch-equivalent wafers this year, a typical 10 percent annual increase. The biggest share—two million wafers—will use its planar 28nm processes for which it is boosting capacity 15 percent this year.

TSMC has taped out nearly 800 chips using flavors of its 28nm process. It has shipped 4.5 million 28nm wafers to date, clearly a big sweet spot it aims to defend.

Globalfoundries hopes to capture many of those customers starting this year with 22nm FD-SOI, a lower cost, lower power alternative with similar performance to TSMC’s 16nm FinFET node. TSMC claims its 22nm process provides an easier migration path from 28nm while FD-SOI requires redesigned intellectual property cores.

“Bulk semiconductor technology has been enhanced for 30 years and is used by Intel and Samsung,” the world’s two largest chip makers, said Mark Liu, TSMC’s co-chief executive in a brief interview after a keynote here. “FD-SOI will always be the technology of the future,” he quipped.

The news comes the same day NXP announced it will use FD-SOI for multiple future processors. So far, a total of just 10,000 FD-SOI wafers/month are shipping from all fabs including Globalfoundries and STMicroelectronics, said Sam Wang, a chip analyst for Gartner.

Globalfoundries may be slightly ahead in timing, ramping its 22nm FD-SOI process now with Sony image sensors in production. TSMC said its 22nm process will be in production next year, aimed at 5G RF and other mobile chips including image processors and components for wearables and the Internet of Things.

The 22nm FD-SOI node sports similar specs to TSMC’s 22nm process, “but it does not have the comprehensive IP ecosystem… and the manufacturing track record we have,” said B.J. Woo, vice president of business development at TSMC.

TSMC also plans an ultra-low power version of its 12nm FinFET process, supporting 0.5V operation and starting risk production before June. It will likely be positioned as a competitor to the 12nm FD-SOI process Globalfoundries announced last year but is not expected in production until 2019.

The ultra-low power TSMC 22nm process should deliver a 20 percent area shrink and either 0.45x the power or 1.32x the speed of its 28 HPM process, Woo said. Compared to its 28 HPC+ process, the 22nm is a direct optical shrink with better transistors and 0.6 Vdd operation offering 10 percent smaller size and 35 percent less power or 15 percent more speed, she said.

TSMC’s 22nm node uses the same mask counts, design rules, SRAM bit cells and I/O devices as its 28HPC+ node. Designers only need to adopt its boosted transistors and re-characterize foundation IP to ensure they meet new margins, Woo said.

“The migration effort is really different [from FD-SOI]—it’s a day and night difference,” said Jack Sun, a vice president of R&D at TSMC.

TSMC’s Liu said the foundry expects 70 tape outs of IoT chips this year across its family of ultra-low power processes that range from 55 to 28nm. The 40nm ULP process has been characterized for near-threshold operation driving energy efficiency to 11 microamps/MHz, he said.


  TSMC held a 3nm Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in STSP last December 29.  Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) held a 3nm Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP) last December 29, bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the company’s advanced manufacturing.  TSMC has laid a strong foundation for 3nm technology and capacity expansion, with Fab 18 located in the STSP serving as the company’s GIGAFAB facility producing 5nm and 3nm process technology. TSMC announced that 3nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. The company estimates that 3nm technology will create end products with a market value of $1.5 trillion within five years of volume production.  Phases 1 through 8 of TSMC Fab 18 each have cleanroom area of 58,000sqm, approximately double the size of a standard logic fab. TSMC’s total investment in Fab 18 will exceed NT$1.86 trillion, creating more than 23,500 construction jobs and over 11,300 high-tech direct job opportunities. In addition to expanding 3nm capacity in Taiwan, TSMC is also building 3nm capacity at its Arizona site.  TSMC also announced that its global R&D Center in the Hsinchu Science Park will officially open in the second quarter of 2023, to be staffed by 8,000 R&D personnel. TSMC is also making preparations for its 2nm fabs, which will be located in the Hsinchu and Central Taiwan Science Parks, with a total of six phases proceeding as planned.  TSMC Chairman Dr. Mark Liu presided over the 3nm Volume Production and Capacity Expansion Ceremony, and notable guests at the event included Vice Premier Shen Jong-chin, Minister of Economic Affairs Wang Mei-hua, Minister of Science and Technology Wu Tsung-tsong, Tainan City Mayor Huang Wei-che, STSP Administration Bureau Director-General Su Chen-kang, Fu Tsu Construction Chairman Cliff Lin, United Integrated Services Chairman Belle Lee, National Cheng Kung University President Dr. Jenny Su, Chang Chun Petrochemical President Chih-Chuan Tsai, Kuang Ming Enterprise Co. Vice Chairman Eric Lin, and Applied Materials Group Vice President Erix Yu, as well as representatives from TSMC’s construction partners, materials and equipment suppliers, the Taiwan Semiconductor Industry Association and academic institutions.  “TSMC is maintaining its technology leadership while investing significantly in Taiwan, continuing to invest and prosper with the environment. This 3nm Volume Production and Capacity Expansion Ceremony demonstrates that we are taking concrete action to develop advanced technology and expand capacity in Taiwan,” Dr. Liu said at the ceremony. “We aim to grow together with our upstream and downstream supply chain and develop future talent from design to manufacturing, packaging and testing, equipment, and materials to provide the most competitive advanced process technology and reliable capacity for the world and drive technology innovation in the future.”  TSMC is committed to flourishing with the natural environment through green manufacturing, and all of TSMC’s construction in the STSP follows Taiwan’s EEWH and the U.S. LEED green building certification standards. The facilities will also use water resources from the TSMC STSP Reclaimed Water Plant to gradually reach the company’s target of using 60% reclaimed water by 2030. Once volume production begins, Fab 18 will use 20% renewable energy to eventually reach the sustainability goal of 100% renewable energy and zero emissions by 2050.  TSMC’s 3nm process is the most advanced semiconductor technology in both power, performance, and area (PPA) and in transistor technology, and a full-node advance from the 5nm generation. Compared with the 5nm (N5) process, TSMC’s 3nm process offers up to 1.6X logic density gain and 30-35% power reduction at the same speed, and supports the innovative TSMC FINFLEX? architecture.
2023-01-04 09:32 阅读量:1405
TSMC’s announcement last week that it expects its quarterly sales to decline precipitously quarter to quarter put the chip foundry market on notice as it begins what is expected to be a challenging year.TSMC (Hsinchu, Taiwan) said that it expects sales to decline nearly 14% quarter to quarter to between $7.3 billion and $7.4 billion. It would be the largest quarter-to-quarter sales decline for the world’s leading foundry since 2009.The expected shortfall has been largely blamed in weaker-than-expected sales of Apple’s newest iPhones, which features Apple-designed processors built by TSMC. But the weak sales guidance is also indicative of larger challenges facing the foundry industry, according to Bill McClean, a veteran semiconductor analyst and president of market research firm IC Insights.“The foundry market is in a difficult position in 2019,” McClean told EE Times in an email exchange. IC Insights said earlier this month that nearly all of the pure-play foundry industry’s growth in 2018 came from Chinese firms. TSMC alone saw its revenue from China increase by 61% last year, according to the firm.“Apple represented about 22% of TSMC’s sales last year, and we all know that Apple has backed down its expectations for this year,” McClean said. Apple earlier this month cut its sales forecast for the first time since 2002.Much of the growth in foundry business from China came from the cryptocurrency business, a market that has softened considerably amid a plunge in cryptocurrency prices, McClean said.According to McClean, the pure-play foundry market also faces technology challenges. “TSMC is the only pure-play foundry offering leading-edge feature-sized technology,” he said. “All of the other pure-play foundries are now labeling themselves as specialty foundries, offering embedded memory, image sensor, SOI, etc. technology at relaxed feature sizes.”The result has been a glut in specialty foundry capacity, according to McClean. Both TSMC and Samsung — an integrated device manufacturer that also offers leading-edge foundry capacity — are also players in the specialty foundry market, he said.“It is so bad now that most foundries talk about overcapacity at the 28-nm node lasting for a couple of years,” McClean said.IC Insights is currently forecasting that the foundry market will grow about 2% in 2019, the same growth rate that the firm has projected for the semiconductor industry as a whole.TSMC reported sales of $9.4 billion for the fourth quarter of 2018, up 10.7% compared to the third quarter of 2018 and up 2% compared to the fourth quarter of 2017. TSMC reported that 7-nm revenue was 23% of the company’s fourth-quarter total, while 10 nm accounted for 6% and 16/20 nm accounted for 21%.
2019-01-23 00:00 阅读量:1333
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